isppac-powr607 Lattice Semiconductor Corp., isppac-powr607 Datasheet - Page 2

• Manufacturer Part Number: isppac-powr607
• Description: N-system Programmable Power Supply Supervisor, Reset Generator And Watchdog Tim
• Manufacturer: Lattice Semiconductor Corp.

Pin Descriptions
Lattice Semiconductor
ate delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using LogiBuilder™, an easy-
to-learn language integrated into the PAC-Designer
of any of the analog input channel comparators or the digital inputs.
Figure 4-1. ispPAC-POWR607 Block Diagram
Number
11, 12
30
31
27
26
23
22
20
29
28
IN1_PWRDN
IN_OUT3
IN_OUT4
IN_OUT5
IN_OUT6
IN_OUT7
HVOUT1
HVOUT2
Name
GND
IN2
IN1_PWRDN
Ground
Open Drain Output
FET Gate Driver
Open Drain Output
FET Gate Driver
Digital Input
Open Drain Output
Digital Input
Open Drain Output
Digital Input
Open Drain Output
Digital Input
Open Drain Output
Digital Input
Open Drain Output
Digital Input
Digital Input
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
IN2
Pin Type
9
9
9
9
9
Power Down
4 Timers
Logic
2
2
2
2
2
2
2
®
software. Control sequences are written to monitor the status
Ground
0V to 10V
0V to 9V
0V to 10V
0V to 9V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
4-2
VCC
Voltage Range
ispPAC-POWR607
JTAG Interface
16 Macrocells
28 Inputs
PLD
3
3
Ground
Open-Drain Output 1
High-voltage FET Gate Driver 1
Open-Drain Output 2
High-voltage FET Gate Driver 2
PLD Input 3
Open Drain Output 3
PLD Input 4
Open Drain Output 4
PLD Input 5
Open Drain Output 5
PLD Input 6
Open Drain Output 6
PLD Input 7
Open Drain Output 7
PLD Logic Input 1.
should be pulled down with a 10k Ω resistor.
PLD Logic Input 2. When not used, this pin
should be tied to GND.
ispPAC-POWR607 Data Sheet
HVOUT1
HVOUT2
IN_OUT3
IN_OUT4
IN_OUT5
IN_OUT6
IN_OUT7
1
Description
4, 5
When not used, this pin