isppac-powr607 Lattice Semiconductor Corp., isppac-powr607 Datasheet - Page 14

• Manufacturer Part Number: isppac-powr607
• Description: N-system Programmable Power Supply Supervisor, Reset Generator And Watchdog Tim
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 4-10. ispPAC-POWR607 PLD Architecture
Macrocell Architecture
The macrocell shown in Figure 4-11 is the heart of the PLD. The basic macrocell has five product terms that feed
the OR gate and the flip-flop. The flip-flop in each macrocell is independently configured. It can be programmed to
function as a D-Type or T-Type flip-flop. Combinatorial functions are realized by bypassing the flip-flop. The polarity
control and XOR gates provide additional flexibility for logic synthesis. The flip-flop’s clock is driven from the com-
mon PLD clock that is generated by dividing the 8 MHz master clock (MCLK) by 32. The macrocell also supports
asynchronous reset and preset functions, derived from either product terms or the power-on reset signal. The
resources within the macrocells share routing and contain a product term allocation array. The product term alloca-
tion array greatly expands the PLD’s ability to implement complex logical functions by allowing logic to be shared
between adjacent blocks and distributing the product terms to allow for wider decode functions. All the digital inputs
are registered by MCLK and all VMON comparator outputs are registered using the PLD Clock to synchronize them
to the PLD logic.
IN1_PWRDN
IN2
VMON[1:6]
VCC
Sleep/
Wake
Logic
Timer0
Timer1
Timer2
Timer3
6
4
Register
Register
MCLK
Input
Input
Feedback
Output
16
R
P
I
81 P-Terms
PLD Clock
AND Array
28 Inputs
16
PLD_PWRDN
4-14
16
81
Reset
16 Macrocell
Timer Clock
81 P-Terms
Generic
Logic
Block
GLB
ispPAC-POWR607 Data Sheet
HVOUT[1:2]
IN_OUT[3:7]