isppac-clk5620v-01t48c Lattice Semiconductor Corp., isppac-clk5620v-01t48c Datasheet - Page 40

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isppac-clk5620v-01t48c

Manufacturer Part Number
isppac-clk5620v-01t48c
Description
In-system Programmable, Zero-delay Clock Generator With Universal Fan-out Buffer
Manufacturer
Lattice Semiconductor Corp.
Datasheet
Lattice Semiconductor
Pin Descriptions (Continued)
VCCD
GNDD
VCCJ
REFA+
REFA-
REFB+
REFB-
REFSEL
REFVTT
FBKA+
FBKA-
FBKB+
FBKB-
FBKSEL
FBKVTT
TDO
TDI
TCK
TMS
LOCK
SGATE
GOE
OEX
OEY
PS0
PS1
PLL_BYPASS PLL Bypass
RESET
TEST1
TEST2
n/c
Reserved
1. Internal pull-down resistor.
2. Internal pull-up resistor.
Pin Name
Digital Core VCC
Digital GND
JTAG interface VCC
Clock Reference A positive input
Clock Reference A negative input
Clock Reference B positive input
Clock Reference B negative input
Clock Reference Select input (LVCMOS)
Termination voltage for reference inputs
Clock feedback A positive input
Clock feedback A negative input
Clock feedback B positive input
Clock feedback B negative input
Clock feedback select input (LVCMOS)
Termination voltage for feedback inputs
JTAG TDO Output line
JTAG TDI Input line
JTAG Clock Input
JTAG Mode Select
PLL Lock indicator, LOW indicates PLL lock
Synchronous output gate
Global Output Enable
Output Enable 1
Output Enable 2
Profile Select 0
Profile Select 1
Reset PLL
Test Input 1 - connect to GNDD
Test Input 2 - connect to GNDD
No internal connection
Factory use only - Do not connect
Description
40
Pin Type
Output
Output
Power
Power
Power
Input1
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
GND
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
n/a
n/a
1
2
2
1
1
1
1
1
1
ispClock5600 Family Data Sheet
ispClock5610
48 TQFP
24, 33
23, 48
36
18
19
20
15
16
17
35
39
38
37
34
40
42
21
22
44
43
47
41
46
45
Pin Number
1, 2, 23, 24, 25, 26, 27,
28, 29, 48, 49, 50, 75,
76, 77, 78, 79, 94, 97,
ispClock5620
80, 81, 95, 96
98, 99, 100
100 TQFP
47, 71
46, 93
74
38
39
42
41
43
40
32
33
36
35
37
34
73
84
83
82
72
85
87
44
45
89
88
92
86
91
90

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