wm9081 Wolfson Microelectronics plc, wm9081 Datasheet - Page 68

• Manufacturer Part Number: wm9081
• Description: Mono Dac With 2.6w Class Ab/d Speaker Driver, Dynamic Range Controller And Retune Mobile Parametric Equalizer
• Manufacturer: Wolfson Microelectronics plc

WM9081
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OPCLK CONTROL
A clock output (OPCLK) derived from CLK_SYS may be output on the MCLK pin. This clock is
enabled by register bit CLK_OP_ENA, and its frequency is controlled by CLK_OP_DIV.
This output is only supported when MCLK is not selected as an input to the WM9081.
Table 39 OPCLK Control
FREQUENCY LOCKED LOOP (FLL)
The integrated FLL can be used to generate CLK_SYS from a wide variety of different reference
sources and frequencies. The FLL can use either MCLK, BCLK or LRCLK as its reference, which
may be a high frequency (eg. 12.288MHz) or low frequency (eg. 32.768kHz) reference. The FLL is
tolerant of jitter and may be used to generate a stable CLK_SYS from a less stable input signal. The
FLL characteristics are summarised in “Electrical Characteristics”.
Note that the FLL can be used to generate a free-running clock in the absence of an external
reference source. This is described in the “Free-Running FLL Clock” section below.
The FLL is enabled using the FLL_ENA register bit. Note that, when changing FLL settings, it is
recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other
register settings have been updated. When changing the input reference frequency F
recommended that the FLL be reset by setting FLL_ENA to 0.
The field FLL_CLK_REF_DIV provides the option to divide the input reference (MCLK, BCLK or
LRCLK) by 1, 2, 4 or 8. This field should be set to bring the reference down to 13.5MHz or below. For
best performance, it is recommended that the highest possible frequency - within the 13.5MHz limit -
should be selected.
The field FLL_CTRL_RATE controls internal functions within the FLL; it is recommended that only
the default setting be used for this parameter. FLL_GAIN controls the internal loop gain and should
be set to the recommended value.
The FLL output frequency is directly determined from FLL_FRATIO, FLL_OUTDIV and the real
number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the
fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the
field FLL_FRAC. It is recommended that FLL_FRAC is enabled at all times.
The FLL output frequency is generated according to the following equation:
R12 (0Ch)
Clock
Control1
R14 (0Eh)
Clock
Control3
REGISTER
ADDRESS
12:10
BIT
5
CLK_OP_DIV
[2:0]
CLK_OP_ENA
LABEL
DEFAULT
000
0
OPCLK Clock Divider
000 = CLK_SYS
001 = CLK_SYS / 2
010 = CLK_SYS / 3
011 = CLK_SYS / 4
100 = CLK_SYS / 6
101 = CLK_SYS / 8
110 = CLK_SYS / 12
111 = CLK_SYS / 16
Clock Output Enable
0 = Disabled
1 = Enabled
This bit enables OPCLK output on
the MCLK pin.
Frequency is set by CLK_OP_DIV.
DESCRIPTION
PP, Rev 3.0, April 2009
Pre-Production
REF
, it is
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