xwm8722eds ETC-unknow, xwm8722eds Datasheet - Page 12

• Manufacturer Part Number: xwm8722eds
• Description: Stereo Dac With Integrated Tone Generator And Line/variable Level Outputs
• Manufacturer: ETC-unknow

WM8722
MODES OF OPERATION
The software control interface may be operated using either a 3-wire (SPI-compatible) or 2-wire MPU
interface. Selection of interface format is achieved by monitoring the state of BUSY pin at power up.
In 3-wire mode, MD is used for the program data, MC is used to clock in the program data and
LATCH is used to latch in the program data. In 2-wire mode, MD is used for serial data and MC is
used for serial clock. In 2-wire mode, the LATCH pin allows the user to select one of two addresses.
SELECTION OF SERIAL CONTROL MODE
The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved
by setting the state of the BUSY pin at power-up with a weak, external pull-up or pull-down resistor
(typically 10k). This pin is an input at power up, and its state selects the type of input format. The
value input at power-up is sampled and stored internally. This allows the BUSY pin to be used as an
output when tone generation has been enabled. This stored value is only reset when the device is
powered off.
Table 3 Control Interface Mode Selection
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
The WM8722 can be controlled using a 3-wire serial interface. MD is used for the program data, MC
is used to clock in the program data and LATCH is use to latch in the program data. The 3-wire
interface protocol is shown in Figure 7. Please note that latch is edge sensitive not level sensitive.
Data is latched on a rising edge of latch.
Figure 7 3-Wire Serial Interface
2-WIRE SERIAL CONTROL MODE
The WM8722 supports a 2-wire MPU serial interface. The device operates as a slave device only.
The WM8722 has one of two slave addresses that are selected by setting the state of pin 5,
(LATCH).
Figure 8 2-Wire Serial Interface
GENERATION NOT ENABLED)
LATCH
MD
MC
BUSY PIN (TONE
MC
MD
START
0
1
B15
R ADDR
B14
B13
R/W
B12
B11
ACK
INTERFACE
B10
FORMAT
3 wire
2 wire
B9
DATA B15-8
B8
B7
B6
ACK
B5
B4
DATA B7-0
B3
B2
AI Rev 2.1 June 2001
Advanced Information
B1
ACK
B0
STOP
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