wm8770 Wolfson Microelectronics plc, wm8770 Datasheet
wm8770
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wm8770 Summary of contents
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... CODEC with Volume Control DESCRIPTION The WM8770 is a high performance, multi-channel audio codec. The WM8770 is ideal for surround sound processing applications for home hi-fi, automotive and other audio visual equipment. A stereo 24-bit multi-bit sigma delta ADC is used with an eight stereo channel input selector. Each channel has analogue domain mute and programmable gain control ...
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... WM8770 DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................6 ELECTRICAL CHARACTERISTICS ......................................................................7 TERMINOLOGY ............................................................................................................ 8 MASTER CLOCK TIMING......................................................................................9 DIGITAL AUDIO INTERFACE – MASTER MODE ......................................................... 9 DIGITAL AUDIO INTERFACE – SLAVE MODE .......................................................... 11 MPU INTERFACE TIMING .......................................................................................... 12 INTERNAL POWER ON RESET CIRCUIT ..........................................................14 DEVICE DESCRIPTION ...
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... VMIDDAC 40 VOUT2R 39 38 GR1 37 VOUT2L DACREFP1 36 35 VOUT1R VOUT1L 34 AVDD2 MOISTURE SENSITIVITY PACKAGE 64-lead TQFP o C (Pb-free) 64-lead TQFP o C (tape and reel, Pb-free) WM8770 PEAK SOLDERING TEMPERATURE LEVEL o MSL3 260 C o MSL3 260 C PD Rev 4.2 March 2008 3 ...
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... WM8770 PIN DESCRIPTION PIN NAME 1 AIN1L Analogue Input 2 AIN1R Analogue Input 3 AIN2L Analogue Input 4 AIN2R Analogue Input 5 AIN3L Analogue Input 6 AIN3R Analogue Input 7 AIN4L Analogue Input 8 AIN4R Analogue Input 9 AIN5L Analogue Input 10 AIN5R Analogue Input 11 AIN6L Analogue Input 12 AIN6R Analogue Input ...
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... Master DAC and ADC clock; 256, 384, 512 or 768fs (fs = word clock frequency) Serial interface clock (5V tolerant) Serial interface data (5V tolerant) Serial interface Latch signal (5V tolerant) Device reset input (mutes DAC outputs, resets gain stages to 0dB) (5V tolerant) WM8770 DESCRIPTION PD Rev 4.2 March 2008 5 ...
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... WM8770 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process therefore generically susceptible to damage from excessive static voltages ...
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... A-weighted, 0dB gain @ fs = 96kHz A-weighted, -60dB full scale input kHz, 0dBFs 1kHz, -1dBFs 1kHz Input 1kHz Input 1kHz Input, 0dB gain PSRR 1kHz 100mVpp 20Hz to 20kHz 100mVpp WM8770 MIN TYP MAX 0.8 2.0 0.1 x DVDD AVDD/2 50k 1.0 x AVDD/5 100 106 106 100 ...
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... WM8770 Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T otherwise stated. PARAMETER Analogue input (AIN) to Analogue output (VOUT) (Load=10kΩ, 50pF, gain = 0dB) Bypass Mode 0dB Full scale output voltage SNR (Note 1) THD Power Supply Rejection Ratio Mute Attenuation Supply Current Analogue supply current ...
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... MCLKH t MCLKY 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless A SYMBOL TEST CONDITIONS t MCLKH t MCLKL t MCLKY After MCLK stopped After MCLK re-started DSP/ ENCODER/ DECODER WM8770 MIN TYP MAX UNIT 1000 ns 40:60 60: µs 0.5 1 MCLK cycle PD Rev 4.2 March 2008 ...
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... WM8770 BCLK (Output) ADCLRC/ DACLRC (Outputs) DOUT DIN1/2/3/4 Figure 3 Digital Audio Data Timing – Master Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T otherwise stated. PARAMETER SYMBOL Audio Data Input Timing Information ADCLRC/DACLRC t propagation delay from BCLK falling edge DOUT propagation delay ...
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... DH BCLK rising edge DOUT propagation delay t DD from BCLK falling edge Table 3 Digital Audio Data Timing – Slave Mode Note: ADCLRC and DACLRC should be synchronous with MCLK, although the WM8770 interface is tolerant of phase variations or jitter on these signals. w DSP ENCODER/ DECODER t t ...
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... WM8770 MPU INTERFACE TIMING t t RCSU RCHO RESETB Figure 6 SPI Compatible Control Interface Input Timing Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T otherwise stated. PARAMETER CE to RESETB hold time RESETB to CL setup time CL rising edge to CE rising edge CL pulse cycle time ...
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... 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless A SYMBOL t RCES t RCLH t DSU t DHO SCH t SCL t SCY t CH D15 t CH D15 MIN TYP MAX Rev 4.2 March 2008 WM8770 UNIT ...
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... INTERNAL POWER ON RESET CIRCUIT Figure 9 Internal Power On Reset Circuit Schematic The WM8770 includes an internal Power On Reset Circuit which is used to reset the digital logic into a default state after power up. Figure 9 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD. The circuit monitors DVDD and VMIDADC and asserts PORB low if DVDD or VMIDADC are below the minimum threshold Vpor_off ...
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... Production Data Figure 10 Typical Power up sequence where DVDD is powered before AVDD. Figure 11 Typical Power up sequence where AVDD is powered before DVDD Typical POR Operation (typical values, not tested) SYMBOL V pora V porr V pora_off V pord_off w MIN TYP 0.5 0.7 0.5 0.7 1.0 1.4 0.6 0.8 WM8770 MAX UNIT 1.0 V 1.1 V 2 Rev 4.2 March 2008 15 ...
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... WM8770 In a real application the designer is unlikely to have control of the relative power up sequence of AVDD and DVDD. Using the POR circuit to monitor VMIDADC ensures a reasonable delay between applying power to the device and Device Ready. Figure 10 and Figure 11 show typical power up scenarios in a real system. Both AVDD and DVDD must be established and VMIDADC must have reached the threshold Vporr before the device is ready and can be written to ...
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... CE, CL, DI and RESETB are 5V tolerant with TTL input thresholds, allowing the WM8770 to used with DVDD = 3.3V and be controlled by a controller with 5V output. Operation using system clock of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided. In Slave mode selection between clock rates is automatically controlled ...
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... If there is a greater than 32 clocks error the interface is disabled and maintains the output level at the last sample. The master clock must be synchronised with ADCLRC/DACLRC, although the WM8770 is tolerant of phase variations or jitter on this clock. Table 6 shows the typical master clock frequency inputs for the WM8770. ...
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... Table 8 Master Mode ADC/DACLRC Frequency Selection BCLK is also generated by the WM8770. The frequency of BCLK depends on the mode of operation. In 128/192fs modes (DACRATE=000 or 001) BCLK = MCLK/2. In 256/384/512fs modes (ADCRATE/DACRATE=010 or 011 or 100) BCLK = MCLK/4. However if DSP mode is selected as the audio interface mode then BCLK=MCLK. This is to ensure that there are sufficient BCLKs to clock in all eight channels ...
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... MASTER AND SLAVE MODES The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In both Master and Slave modes DACDAT is always an input to the WM8770 and ADCDAT is always an output. The default is Slave mode. In Slave mode (MS=0) ADCLRC, DACLRC and BCLK are inputs to the WM8770 (Figure 12). ...
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... In Master mode (MS=1) ADCLRC, DACLRC and BCLK are outputs from the WM8770 (Figure 13). ADCLRC, DACLRC and BITCLK are generated by the WM8770. DIN1/2/3/4 are sampled by the WM8770 on the rising edge of BCLK so the controller must output DAC data that changes on the falling edge of BCLK. ADCDAT is output on DOUT and changes on the falling edge of BCLK. By setting control bit BCLKINV the polarity of BCLK may be reversed so that DIN1/2/3/4 are sampled on the falling edge of BCLK and DOUT changes on the rising edge of BCLK ...
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... Figure 14 Left Justified Mode Timing Diagram RIGHT JUSTIFIED MODE In right justified mode, the LSB of DIN1/2/3/4 is sampled by the WM8770 on the rising edge of BCLK preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the falling edge of BCLK preceding a ADCLRC transition and may be sampled on the rising edge of BCLK ...
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... Production Data DSP EARLY MODE In DSP early mode, the MSB of DAC channel 1 left data is sampled by the WM8770 on the second rising edge on BCLK following a DACLRC rising edge. DAC channel 1 right and DAC channels 2, 3 and 4 data follow DAC channel 1 left data (Figure 17). ...
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... WM8770 DSP LATE MODE In DSP late mode, the MSB of DAC channel 1 left data is sampled by the WM8770 on the first BCLK rising edge following a DACLRC rising edge. DAC channel 1 right and DAC channels 2, 3 and 4 data follow DAC channel 1 left data (Figure 19). ...
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... CCB INTERFACE MODE CCB Interface mode allows multiple devices to be controlled off a common 3-wire bus. Each device on the 3-wire bus has its own identifying address. The WM8770 supports write only CCB interface mode used for the device address and program data and CL is used to clock in the address and data on DI ...
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... Note: If 32-bit mode is selected in right justified mode, the WM8770 defaults to 24 bits. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive bit data, the WM8770 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. ...
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... Rate MUTE MODES The WM8770 has individual mutes for each of the four DAC channels. Setting MUTE for a channel will apply a ‘soft’ mute to the input of the digital filters of the channel muted. DMUTE[0] mutes DAC channel 1, DMUTE[1] mutes DAC channel 2, DMUTE[2] mutes DAC channel 3 & DMUTE[3] mutes DAC channel 4 ...
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... WM8770 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 Figure 24 Application and Release of Soft Mute Figure 24 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards V with a time constant of approximately 64 input samples ...
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... Emphasis modes at different sample rates. POWERDOWN MODE AND ADC/DAC DISABLE Setting the PDWN register bit immediately powers down the WM8770, including the references, overriding all other powerdown control bits. All trace of the previous input samples are removed, but all control register settings are preserved. When PDWN is cleared the digital filters will be reinitialised ...
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... WM8770 INFINITE ZERO DETECT ENABLE Setting the IZD register bit will enable the internal infinite zero detect function: REGISTER ADDRESS 10011 DAC Channel Control With IZD enabled, applying 1024 consecutive zero input samples to all 8 DAC channels will cause all DAC outputs to be muted. Mute will be removed as soon as any channel receives a non-zero input. ...
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... Attenuation data for Right channel DACL3 in 1dB steps. See Table 11 (0dB) DACR3 zero cross detect enable 0 0: zero cross disabled 1: zero cross enabled Not latched Controls simultaneous update of all Attenuation Latches 0: Store R3A in intermediate latch (no change to output) 1: Store R3A and update attenuation on all channels. WM8770 DESCRIPTION PD Rev 4.2 March 2008 31 ...
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... WM8770 REGISTER BIT LABEL ADDRESS 00110 6:0 L4A[6:0] Analogue Attenuation 7 L4ZCEN DACL4 8 UPDATE 00111 6:0 R4A[6:0] Analogue Attenuation 7 R4ZCEN DACR4 8 UPDATE 01000 6:0 MASTA[6:0] Master Analogue 7 MZCEN Attenuation (all channels) 8 UPDATE Table 10 Attenuation Register Map Each DAC channel volume can be controlled digitally in an analogue volume stage after the DAC. ...
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... Store LDA3 and update attenuation on all channels. 11111111 Digital Attenuation data for Right channel DACR3 in 0.5dB steps. See Table 12 (0dB) Controls simultaneous update of all Attenuation Latches Not latched 0: Store RDA3 in intermediate latch (no change to output) 1: Store RDA3 and update attenuation on all channels. WM8770 DESCRIPTION PD Rev 4.2 March 2008 33 ...
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... WM8770 REGISTER BIT LABEL ADDRESS 01111 7:0 LDA4[7:0] Digital Attenuation 8 UPDATE DACL4 10000 7:0 RDA4[7:0] Digital Attenuation 8 UPDATE DACR4 10001 7:0 MASTDA[7:0] Master Digital 8 UPDATE Attenuation (all channels) L/RDAX[7:0] Table 12 Digital Volume Control Attenuation Levels The Digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume ...
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... Setting LRBOTH will write the same gain value to RAG[4:0] and LAG[4:0] ATTENUATION LEVEL 0 -12dB : : 01100 0dB : : 11111 +19dB DEFAULT DESCRIPTION 00000000 Bit DAC 0 DAC1L 1 DAC1R 2 DAC2L 3 DAC2R 4 DAC3L 5 DAC3R 6 DAC4L 7 DAC4R DESCRIPTION PD Rev 4.2 March 2008 WM8770 Phase 1 = invert 1 = invert 1 = invert 1 = invert 1 = invert 1 = invert 1 = invert 1 = invert 35 ...
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... WM8770 ADC HIGHPASS FILTER DISABLE The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled using software control bit ADCHPD. REGISTER ADDRESS 10110 ADC control ADC INPUT MUX AND POWERDOWN CONTROL REGISTER ADDRESS 11011 ADC Mux and ...
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... OUTPD[3:2] 11 MX[0] MX[1] MX[2] MX4[0] MX4[1] WM8770 DESCRIPTION VOUT1 Output select (Figure 25) VOUT2 Output select (see Figure 25) Mixer and EVR Powerdown select 0: mixer and EVR enabled 1: mixer and EVR powered down VOUT3 Output select (see Figure 25) VOUT4 Output select (see Figure 26) ...
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... REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8770 can be configured using the Control Interface. All unused bits should be set to ‘0’. REGISTER B15 B14 B13 B12 B11 B10 B9 ...
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... Attenuation Data for Left channel DACL3 in 1dB steps. Table 11 (0dB) 0 DACR2 Zero Cross Detect Enable 0: zero cross disabled 1: zero cross enabled Not latched Controls simultaneous update of all Attenuation Latches 0: Store DACR3 in intermediate latch (no change to output) 1: Store DACR3 and update attenuation on all channels. WM8770 DESCRIPTION PD Rev 4.2 March 2008 39 ...
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... WM8770 REGISTER BIT LABEL ADDRESS 00110 6:0 L4A[6:0] Analogue Attenuation 7 L4ZCEN DACL4 8 UPDATE 00111 6:0 R4A[6:0] Analogue Attenuation 7 R4ZCEN DACR4 8 UPDATE 01000 6:0 MASTA[6:0] Analogue Master 7 MZCEN Attenuation (all channels) 8 UPDATE 01001 7:0 LDA1[7:0] Digital Attenuation 8 UPDATE DACL1 01010 7:0 RDA1[6:0] Digital Attenuation 8 UPDATE DACR1 01011 ...
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... DAC Output Control PL[3:0] Left Output 0000 Mute 0001 Left 0010 Right 0011 (L+R)/2 0100 Mute 0101 Left 0110 Right 0111 (L+R)/2 WM8770 DESCRIPTION Right PL[3:0] Left Right Output Output Output Mute 1000 Mute Right Mute 1001 Left Right Mute 1010 Right Right Mute ...
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... WM8770 REGISTER BIT LABEL ADDRESS 10100 3:0 DMUTE[3:0] Mute Control 4 MUTEALL 5 RECEN 10101 3:0 DEEMP[3:0] DAC Control 7:4 DZFM[3:0] 1:0 FMT[1:0] 10110 Interface Control 2 LRP 3 BCP 5:4 WL[1:0] 8 ADCHPD w DEFAULT 0000 DAC Channel Soft Mute Enables: 0: mute disabled 1: mute enabled 0 DAC Channel Master Soft Mute. Mutes all DAC channels: ...
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... Setting LRBOTH will write the same gain value to RAG[4:0] and LAG[4:0] 000 ADC left channel input mux control bits 000 ADC right channel input mux control bits 1 Input mux and buffer powerdown 0: Input mux and buffer enabled 1: Input mux and buffer powered down WM8770 DESCRIPTION PD Rev 4.2 March 2008 43 ...
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... WM8770 REGISTER BIT LABEL ADDRESS 11100 2:0 MX1[2:0] Output Mux 5:3 MX2[2:0] and 8:7 OUTPD[1:0] Powerdown Control 11101 2:0 MX3[2:0] Output Mux 4:3 MX4[1:0] and 8:7 OUTPD[3:2] Powerdown Control 11111 [8:0] RESET Software reset Table 15 Register Map Description w DEFAULT 001 VOUT1 Output Select (see Figure 25) 001 VOUT2 Output Select (see Figure 25) ...
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... Figure 28 DAC Digital Filter Ripple – 44.1, 48 and 96kHz 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0.6 0.8 1 Figure 30 DAC Digital filter Ripple - 192kHz TYP MAX UNIT 0.4535fs 0.5fs ±0. 0.444fs 0.487fs ±0. 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Frequency (Fs) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Frequency (Fs) PD Rev 4.2 March 2008 WM8770 0.4 0.45 0.5 0.4 0.45 0.5 45 ...
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... Frequency (Fs) Figure 31 ADC Digital Filter Frequency Response ADC HIGH PASS FILTER The WM8770 has a selectable digital highpass filter to remove DC offsets. The filter response is characterised by the following polynomial. H( 0.9995z 0 -5 -10 -15 0 0.0005 0.001 Frequency (Fs) Figure 33 ADC Highpass Filter Response w 0 ...
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... Figure 38 De-Emphasis Frequency Response (48kHz 0.5 0 -0.5 -1 -1 Figure 35 De-Emphasis Error (32KHz) 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0 Figure 37 De-Emphasis Error (44.1KHz) 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0 Figure 39 De-Emphasis Error (48kHz) WM8770 Frequency (kHz Frequency (kHz Frequency (kHz) PD Rev 4.2 March 2008 ...
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... WM8770 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS w Production Data PD Rev 4.2 March 2008 48 ...
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... AUX1L/R DAC1L/R BYPASSL/R SYSTEM 10uF AUX2L/R AUX 5.1 DAC2L/R 10uF AUX3L/R DAC3L/R WM8770 AINOPL AINVGL AIN1L AIN2L AIN3L AIN7L AIN8L AINOPR AINVGR AIN1R AIN2R AIN3R AIN7R AIN8R 4K MX1[1] 4K MX1[0] 4K MX1[ ...
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... DAC structure used in WM8770 produces much less high frequency output noise than competitors devices). This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment ...
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... B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ACD. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS GAUGE PLANE MAX 1.20 0.15 1.05 0.27 0.20 0. WM8770 DM027.B Θ 0. Rev 4.2 March 2008 51 ...
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... WM8770 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...