wm8987 Wolfson Microelectronics plc, wm8987 Datasheet
wm8987
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wm8987 Summary of contents
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... Volts. Different sections of the chip can also be powered down under software control. The WM8987L is supplied in a very small and thin 4x4mm COL package, ideal for use in ultra-portable and wearable systems. BLOCK DIAGRAM ...
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... WM8987L DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................6 RECOMMENDED OPERATION CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................7 TYPICAL PERFORMANCE....................................................................................9 POWER CONSUMPTION.............................................................................................. 9 HEADPHONE OUTPUT THD VERSUS POWER (TYPICAL)....................................... 10 OUTPUT PGA’S LINEARITY ....................................................................................... 11 SIGNAL TIMING REQUIREMENTS .....................................................................12 SYSTEM CLOCK TIMING............................................................................................ 12 AUDIO INTERFACE TIMING – ...
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... Production Data IMPORTANT NOTICE ..........................................................................................59 ADDRESS.................................................................................................................... 59 w WM8987L PD Rev 4.0 August 2008 3 ...
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... WM8987L PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8987LGECO/V -25°C to +85°C WM8987LGECO/RV -25°C to +85°C Note: Reel quantity = 3,500 w PACKAGE MOISTURE SENSITIVITY LEVEL 28-lead COL QFN (4x4mm) MSL3 (Pb-free) 28-lead COL QFN (4x4mm) MSL3 (Pb-free, tape and reel) Production Data ...
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... Midrail Voltage Decoupling Capacitor Microphone Bias Right Channel Input 2 Left Channel Input 2 Right Channel Input 1 Left Channel Input 1 Control Interface Selection Chip Select / Device Address Selection Control Interface Data Input / 2-wire Acknowledge output Control Interface Clock Input WM8987L DESCRIPTION PD Rev 4.0 August 2008 5 ...
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... WM8987L ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process therefore generically susceptible to damage from excessive static voltages ...
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... L P =5mW O SNR AVDD=HPVDD =3.3V 0dBFS LOUT2-OUT3, ROUT2-OUT3 P Output power is very closely correlated with THD; see below. O THD HPVDD=3.3V, R =32Ω =5mW O HPVDD=3.3V, R =16Ω =5mW O WM8987L MIN TYP MAX 1.0 0.545 22 1 -80 0.01 -70 0.03 88 0.04 AVDD/1.65 -66 -58 0.05 0.13 -62 ...
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... WM8987L Test Conditions DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, T ADCOSR = DACOSR = 1 (64 fs), 24-bit audio data unless otherwise stated. PARAMETER Signal to Noise Ratio (A-weighted) Analogue Reference Levels Midrail Reference Voltage Buffered Reference Voltage Microphone Bias Bias Voltage Bias Current Source Output Noise Voltage Digital Input / Output ...
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... Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power savings, especially in the digital sections of the WM8987L. • Operating mode: Significant power savings can be achieved by always disabling parts of the WM8987L that are not used (e.g. mic pre-amps, unused outputs, DAC, ADC, etc.) Control Register ...
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... WM8987 THD+N v Output Power 100 10 1 0.1 0.01 0.1 1 Output Power (mW) WM8987 THD+N v Output Power Single Ended Headset Drive (AC Coupled 0.1 0.01 0 Output Power (mW) WM8987 THD+N v Output Power Single Ended Headset Drive (Capless 0.1 0.01 0.1 1 Output Power (mW) w BTL Headset Drive 10 100 16ohm 3.3V 16ohm 2.7V 16ohm 1.8V 32ohm 3.3V 32ohm 2.7V 32ohm 1.8V 100 16ohm 3 ...
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... Output PGA Gain Step Size 1.50 1.25 1.00 0.75 0.50 0.25 0. XXXVOL Register Setting (binary XXXVOL Register Setting (binary) WM8987L ROUT1 LOUT2 ROUT2 MONOOUT 100 110 120 130 ROUT1 LOUT2 ROUT2 MONOOUT 100 110 120 130 PD Rev 4.0 August 2008 11 ...
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... WM8987L SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 1 System Clock Timing Requirements Test Conditions CLKDIV2=0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse width high MCLK System clock pulse width low ...
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... C, Slave Mode 48kHz, MCLK = 256fs, 24-bit data, unless A SYMBOL t BCY t BCH t BCL t LRSU t LRH MIN TYP MAX 3 3 50:50 T MCLKDS BCL LRSU DS LRH t DH MIN TYP MAX Rev 4.0 August 2008 WM8987L UNIT UNIT ...
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... WM8987L CONTROL INTERFACE TIMING – 3-WIRE MODE SCLK SDIN Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time ...
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... C, Slave Mode 48kHz, MCLK = 256fs, 24-bit data, unless A SYMBOL MIN 600 2 t 600 3 t 600 4 t 100 600 WM8987L TYP MAX UNIT 526 kHz 300 ns 300 ns ns 900 Rev 4.0 August 2008 15 ...
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... AVDD Figure 6 Internal Power on Reset Circuit Schematic The WM8987L includes an internal Power-On-Reset Circuit, as shown below, which is used to reset the digital logic into a default state after power up. The power on reset circuit is powered from DCVDD and monitors DCVDD and AVDD. It asserts PORB low if DCVDD or AVDD are below a minimum threshold ...
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... The digital filters used for recording and playback are optimised for each sampling rate used. To allow full software control over all its features, the WM8987L offers a choice wire MPU control interface fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs ...
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... WM8987L As an example, the WM8987L can be set up to convert one differential and one single ended mono signal by applying the differential signal to LINPUT1/RINPUT1 and the single ended signal to RINPUT2. By setting LINSEL to L-R Differential (see Table 4 LINPUT1 - RINPUT1 and RINSEL to RINPUT2, each mono signal can then be routed to a separate ADC or Bypass pat The signal inputs are biased internally to the reference voltage VREF ...
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... ADC; right data =right ADC 11: left data = right ADC; right data = left ADC BIT LABEL DEFAULT 1 MICB 0 Microphone Bias Enable 0 = OFF (high impedance output MICB MICBIAS = 1.8 x VMID = 0.9 X AVDD internal resistor internal resistor AGND WM8987L DESCRIPTION DESCRIPTION DESCRIPTION PD Rev 4.0 August 2008 19 ...
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... WM8987L PGA CONTROL The PGA matches the input signal level to the ADC input range. The PGA gain is logarithmically adjustable from +30dB to –17.25dB in 0.75dB steps. Each PGA can be controlled either by the user or by the ALC function (see “Automatic Level Control”). When ALC is enabled for one or both channels, then writing to the corresponding PGA control register has no effect ...
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... Production Data ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8987L uses a multi-bit, oversampled sigma-delta ADC for each channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1 ...
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... WM8987L REGISTER R5 (05h) ADC and DAC Control R27 (1Bh) Table 10 ADC Signal Path Control Table 11 ADC High Pass Filter Enable Modes w BIT LABEL ADDRESS 6:5 ADCPOL [1:0] 4 HPOR 0 ADCHPD 5 HPFLREN HPFLREN ADCHPD Production Data DEFAULT DESCRIPTION Polarity not inverted ...
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... LAVU 0 7:0 RADCVOL 11000011 [7:0] ( 0dB ) 8 RAVU 0 WM8987L DESCRIPTION Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -97dB 0000 0010 = -96.5dB ... 0.5dB steps up to 1111 1111 = +30dB Left ADC Volume Update 0 = Store LADCVOL in intermediate latch (no gain change Update left and right channel ...
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... WM8987L AUTOMATIC LEVEL CONTROL (ALC) The WM8987L has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary ...
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... ALC attack (gain ramp-down) time [3:0] (24ms) 0000 = 6ms 0001 = 12ms 0010 = 24ms … (time doubles with every step) 1010 or higher = 6.14s WM8987L DESCRIPTION Note: ensure that LINVOL and RINVOL settings (reg. 0 and 1) are the same before entering this mode. PD Rev 4.0 August 2008 25 ...
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... When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8987L has a noise gate function that prevents noise pumping by comparing the signal level at the L/RINPUT1 and/or L/RINPUT2 pins against a noise gate threshold, NGTH. The noise gate cuts in when: • ...
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... Switching the 3D filter from record to playback or from playback to record may only be done when ADC and DAC are disabled. The WM8987L control interface will only allow MODE3D to be changed when ADC and DAC are disabled (i.e. bits ADCL, ADCR, DACL and DACR in reg. ...
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... The WM8987L output signal paths consist of digital filters, DACs, analogue mixers and output drivers. The digital filters and DACs are enabled when the WM8987L is in ‘playback only’ or ‘record and playback’ mode. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs) ...
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... Production Data GRAPHIC EQUALISER The WM8987L has a digital graphic equaliser and adaptive bass boost function. This function operates on digital audio data before it is passed to the audio DACs. Bass enhancement can take two different forms: • Linear bass control: bass signals are amplified or attenuated by a user programmable gain ...
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... CD with pre-emphasis used in the recording). De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. The WM8987L also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will return to the original setting. This function is enabled by default ...
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... Production Data OUTPUT MIXERS The WM8987L provides the option to mix the DAC output signal with analogue line-in signals from the L/RINPUT1/2, RINPUT1/2 pins or a mono differential input (LINPUT1 – RINPUT1 or LINPUT2 – RINPUT2), selected by DS (see Table 3). The level of the mixed-in signals can be controlled with PGAs (Programmable Gain Amplifiers) ...
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... WM8987L REGISTER ADDRESS R36 (24h) Right Mixer Control (1) R37 (25h) Right Mixer Control (2) Table 23 Right Output Mixer Control The mono mixer differs from the left and right mixers in that the signal from each DAC into the mono mixer is attenuated by 6dB. This is to prevent overloading when left and right DAC signals are mixed to mono ...
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... LABEL DEFAULT 6:0 LOUT2VOL 1111001 [6:0] (0dB) 7 LO2ZC 0 8 LO2VU 0 WM8987L DESCRIPTION DESCRIPTION LOUT2 volume 1111111 = +6dB … (80 steps) 0110000 = -67dB 0101111 to 0000000 = Analogue MUTE Left zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately LOUT2 Volume Update 0 = Store LOUT2VOL in intermediate ...
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... WM8987L REGISTER ADDRESS R41 (29h) ROUT2 Volume R24 (18h) Additional Control (2) Table 26 LOUT2/ROUT2 Volume Control For single-ended operation, the LO2VU and RO2VU bits provide a method to ensure that the left and right channel gains are updated at the same time (irrespective of the time delay between writing to registers R40 and R41) ...
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... Production Data ENABLING THE OUTPUTS The analogue outputs and output mixers of the WM8987L can be separately enabled or disabled as shown in Table 29. REGISTER ADDRESS R26 (1Ah) Power Management (2) Note: All “Enable” bits are OFF Table 29 Analogue Output Control All outputs and mixers are disabled by default. To save power, they should remain disabled whenever possible. Outputs can be enabled at any time, except when VREF is disabled (VR=0), as this may cause pop noise (see “ ...
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... Electrical Characteristic section for timing information. MASTER AND SLAVE MODE OPERATION The WM8987L can be configured as either a master or slave mode device master device the WM8987L generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data transfer on ADCDAT and DACDAT. In slave mode, the WM8987L responds with data to clocks it receives over the digital audio interface ...
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... In device slave mode, Figure 17 and Figure 18 possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse Justified Audio Interface (assuming n-bit word length) WM8987L st nd (mode (mode A) PD Rev 4.0 August 2008 ...
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... WM8987L Figure 15 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master) Figure 16 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master) Figure 17 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave) Figure 18 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave) w Production Data PD Rev 4.0 August 2008 38 ...
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... DACLRC and BCLK to inputs ADCDAT is an output, ADCLRC, DACLRC and BCLK are inputs (slave mode) or outputs (master mode ADCDAT is tristated, ADCLRC, DACLRC and BCLK are inputs WM8987L DESCRIPTION Master / Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode Left/Right channel swap ...
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... WM8987L MASTER MODE ADCLRC AND DACLRC ENABLE In Master mode, by default ADCLRC is disabled when the ADC is disabled and DACLRC is disabled when the DAC is disabled. Register bit LRCM, register 24(18h) bit[2] changes the control so that the ADCLRC and DACLRC are disabled only when ADC and DAC are disabled. This enables the user to use e ...
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... Control Table 37 Clocking and Sample Rate Control The clocking of the WM8987L is controlled using the CLKDIV2, USB, and SR control bits. Setting the CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode. Each value of SR[4:0] selects one combination of MCLK division ratios and hence one combination of sample rates (see next page) ...
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... WM8987L MCLK MCLK ADC SAMPLE RATE CLKDIV2=0 CLKDIV2=1 ‘Normal’ Clock Mode (‘*’ indicates backward compatibility with WM8731) 8 kHz (MCLK/1536) 12.288 MHz 24.576 MHz 8 kHz (MCLK/1536) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 48 kHz (MCLK/256) 48 kHz (MCLK/256) 96 kHz (MCLK/128) 8 ...
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... SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8987L and the R/W bit is ‘0’, indicating a write, then the WM8987L responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’, the WM8987L returns to the idle condition and wait for a new start condition and valid address ...
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... WM8987L The WM8987L has two possible device addresses, which can be selected using the CSB pin. CSB STATE Table 40 2-Wire MPU Interface Address Selection POWER SUPPLIES The WM8987L can use up to four separate power supplies: • AVDD / AGND: Analogue supply, powers all analogue functions except the headphone drivers. ...
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... Table 41 Power Management STOPPING THE MASTER CLOCK In order to minimise power consumed in the digital core of the WM8987L, the master clock may be stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In Standby mode, setting DIGENB will typically provide an additional power saving on DCVDD of 20uA ...
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... ADCOSR set to ‘1’, 64x oversample mode, is not supported in USB mode (USB=1). SAVING POWER AT HIGHER SUPPLY VOLTAGES The analogue supplies to the WM8987L can run from 1.8V to 3.6V. By default, all analogue circuitry on the device is optimized to run at 3.3V. This set-up is also good for all other supply voltages down to 1 ...
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... LMIXSEL[2:0] 001010000 001010000 0 RMIXSEL[2:0] 001010000 001010000 001010000 001010000 001111001 001111001 001111001 PD Rev 4.0 August 2008 WM8987L page ref 20 20 n/a 33 n/a 22, 27, 30 n/a 39 40 19, 20, 30, 35, 46 34, 39, 40 35, 45 ...
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... WM8987L DIGITAL FILTER CHARACTERISTICS The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages. PARAMETER ADC Filter Type 0 (USB Mode, 250fs operation) ...
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... Figure 24 DAC Digital Filter Frequency Response – Type 1 Figure 25 DAC Digital Filter Ripple – Type 1 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 26 DAC Digital Filter Frequency Response – Type 2 Figure 27 DAC Digital Filter Ripple – Type 2 w 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 2 2.5 3 -0.06 0 0.05 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 0 0.05 2 2.5 3 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 -0. 2.5 3 WM8987L 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (Fs) 0.05 0.1 0.15 0.2 Frequency (Fs) PD Rev 4.0 August 2008 0.5 0.5 0.25 49 ...
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... WM8987L 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 28 DAC Digital Filter Frequency Response – Type 3 Figure 29 DAC Digital Filter Ripple – Type 3 ADC FILTER RESPONSES 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 30 ADC Digital Filter Frequency Response – Type 0 0 -20 -40 -60 -80 -100 0 0 ...
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... Figure 35 ADC Digital Filter Ripple – Type 2 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0. 2.5 3 Figure 37 ADC Digital Filter Ripple – Type 3 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 10000 12000 14000 16000 Figure 39 De-emphasis Error (32kHz) WM8987L 0.05 0.1 0.15 0.2 Frequency (Fs) 0.05 0.1 0.15 0.2 Frequency (Fs) 2000 4000 6000 8000 10000 12000 14000 Frequency (Fs) PD Rev 4.0 August 2008 0.25 0.25 16000 51 ...
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... Frequency (Fs) Figure 42 De-emphasis Frequency Response (48kHz) HIGHPASS FILTER The WM8987L has a selectable digital highpass filter in the ADC filter path to remove DC offsets. The filter response is characterised by the following polynomial -10 -15 0 0.0005 0.001 Frequency (Fs) Figure 44 ADC Highpass Filter Response w 0 ...
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... Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 45 Recommended External Components Diagram w WM8987L PD Rev 4.0 August 2008 53 ...
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... WM8987L DRIVING BTL HEADSETS To drive bridge-tied load (BTL) headsets, the analogue outputs should be used as follows: • ROUT1 is the non-inverting right output (HPR+) • LOUT2 is the non-inverting left output (HPL+) • ROUT2 is the inverting right output (HPR-) • OUT3 is the inverting left output (HPL-) This setup is illustrated in Figure 46 ...
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... OUT3 is a pseudo-ground output for the headphone • ROUT1 is unused and should be disabled This setup is illustrated in Figure 47 improving the bass response. Smaller capacitance values will diminish (2π x 16Ω x 220µ WM8987L . c PD Rev 4.0 August 2008 55 ...
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... LOUT2/ROUT2 and OUT3, and therefore no DC blocking capacitors are required. This saves space and material cost in portable applications. However, compared to the single-ended configuration using capacitors, the WM8987L power consumption is higher, due to the additional power consumed in the OUT3 driver recommended to connect the capless headphone outputs only to headphones, and not to the line input of another system ...
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... C1 together with the source impedance of the microphone and the WM8987L input impedance forms an RF filter blocking capacitor to allow the microphone to be biased at a different DC voltage to the MICIN signal. ...
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... WM8987L PACKAGE DIMENSIONS FL: 28 PIN COL QFN PLASTIC PACKAGE BOTTOM VIEW A3 C SIDE VIEW SEATING PLANE Exposed lead Dimensions (mm) Symbols MIN NOM A 0.725 0. 0.203 REF b 0.18 0.23 D 3.95 4.00 4.00 E 3.95 e 0.45 BSC G 0.535 REF 0.100 REF H L 0.40 REF L1 0 ...
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... Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w WM8987L PD Rev 4.0 August 2008 59 ...