wm8988 Wolfson Microelectronics plc, wm8988 Datasheet
wm8988
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wm8988 Summary of contents
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... Volts. Different sections of the chip can also be powered down under software control. The WM8988 is supplied in a very small and thin 4x4mm COL package, ideal for use in hand-held and portable systems. BLOCK DIAGRAM ...
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... WM8988 DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION AND DEVICE MARKING..................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATION CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 POWER CONSUMPTION ....................................................................................10 SIGNAL TIMING REQUIREMENTS .....................................................................11 SYSTEM CLOCK TIMING............................................................................................ 11 AUDIO INTERFACE TIMING – MASTER MODE ......................................................... 11 AUDIO INTERFACE TIMING – SLAVE MODE ............................................................ 12 INTERNAL POWER ON RESET CIRCUIT ...
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... WM8988LGECN/RV -25°C to +85°C Note: Reel quantity = 3,500 w PACKAGE MOISTURE SENSITIVITY LEVEL 28-lead COL QFN MSL3 (4x4x0.55mm, lead-free) 28-lead COL QFN MSL3 (4x4x0.55mm, lead-free) Tape and reel WM8988 PEAK SOLDERING TEMPERATURE 260°C 260°C PD, Rev 4.0, October 2008 3 ...
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... WM8988 PIN DESCRIPTION PIN NO NAME Digital Input 1 MCLK 2 DCVDD Supply 3 DBVDD Supply 4 DGND Supply 5 BCLK Digital Input / Output 6 DACDAT Digital Input 7 LRC Digital Input / Output Digital Output 8 ADCDAT 9 HPCOM Analogue Input 10 LCOM Analogue Input 11 ROUT1 Analogue Output 12 LOUT1 Analogue Output 13 HPGND ...
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... DCVDD must be less than or equal to AVDD and DBVDD. RECOMMENDED OPERATION CONDITIONS PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supplies range Ground w SYMBOL MIN DCVDD 1.42 DBVDD 1.7 AVDD, HPVDD 1.8 DGND,AGND, HPGND WM8988 MIN MAX -0.3V +4.5V DGND -0.3V DBVDD +0.3V AGND -0.3V AVDD +0.3V -25°C +85°C -65°C +150°C TYP MAX UNIT 3.6 3 ...
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... WM8988 ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.5V, DBVDD = 2.4V, AVDD = HPVDD =2. data unless otherwise stated. PARAMETER Analogue Inputs (LINPUT1, RINPUT1, LINPUT2, RINPUT2) to ADC out Full Scale Input Signal Level (for ADC 0dB Input at 0dB Gain) Input Resistance Input Capacitance Signal to Noise Ratio (A-weighted) ...
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... P =5mW O HPCOM=LCOM=0 DACMIXBIAS=1 HPVDD=1.8V, R =16Ω =5mW O HPCOM=LCOM=0 DACMIXBIAS=1 HPVDD=2.4V, R =32Ω =5mW O HPCOM=LCOM=1 DACMIXBIAS=1 HPVDD=2.4V, R =16Ω =5mW O HPCOM=LCOM=1 DACMIXBIAS=1 WM8988 MIN TYP MAX 88 100 -90 -75 -89 -83 -82 -75 -80 -79 -65 -88 -70 -87 -75 -74 -70 -75 -74 ...
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... WM8988 Test Conditions DCVDD = 1.5V, DBVDD = 2.4V, AVDD = HPVDD =2. data unless otherwise stated. PARAMETER SYMBOL Total Harmonic Distortion + Noise Signal to Noise Ratio (A-weighted) Headphone Output Ground noise rejection Line Output Ground Noise Rejection Analogue Reference Levels Midrail Reference Voltage Buffered Reference Voltage Digital Input / Output ...
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... PARAMETER SYMBOL Output HIGH Level Output LOW Level +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio A TEST CONDITIONS +1mA -1mA OL OL WM8988 MIN TYP MAX 0.9×DB VDD 0.1×DBVDD PD, Rev 4.0, October 2008 UNIT ...
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... Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power savings, especially in the digital sections of the WM8988. • Operating mode: Significant power savings can be achieved by always disabling parts of the WM8988 that are not used (e.g. mic pre-amps, unused outputs, DAC, ADC, etc.) SCENARIO ...
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... T MCLKH T MCLKY T MCLKDS o = +25 C, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, A SYMBOL T MCLKL T MCLKH T MCLKY BCLK (Output) LRC (Output) ADCDAT DACDAT t DST WM8988 MIN TYP MAX UNIT 60:40 40:60 MIN TYP MAX UNIT DDA t DHT PD, Rev 4.0, October 2008 ns ns ...
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... WM8988 Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER Bit Clock Timing Information BCLK rise time (10pF load) BCLK fall time (10pF load) BCLK duty cycle (normal mode, BCLK = MCLK/n) BCLK duty cycle (USB mode, BCLK = MCLK) Audio Data Input Timing Information ...
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... C, Slave Mode 48kHz, MCLK = 256fs, 24-bit data, unless A SYMBOL t SCS t SCY t SCL t SCH t DSU t DHO t CSL t CSH t CSS CSL t t CSS SCY t t SCS SCL LSB MIN TYP MAX 80 200 PD, Rev 4.0, October 2008 WM8988 t CSH UNIT ...
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... WM8988 CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) ...
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... AVDD Figure 6 Internal Power on Reset Circuit Schematic The WM8988 includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used to reset the digital logic into a default state after power up. The power on reset circuit is powered from DCVDD and monitors DCVDD and AVDD. It asserts PORB low if DCVDD or AVDD are below a minimum threshold ...
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... The digital filters used for recording and playback are optimised for each sampling rate used. To allow full software control over all its features, the WM8988 offers a choice wire MPU control interface fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs ...
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... LABEL DEFAULT 5 RDCM 0 4 LDCM 0 BIT LABEL DEFAULT WM8988 DESCRIPTION Left Channel Input Select 00 = LINPUT1 01 = LINPUT2 10 = Reserved 11 = L-R Differential (either LINPUT1- RINPUT1 or LINPUT2-RINPUT2, selected by DS) Left Channel Microphone Gain Boost 00 = Boost off (bypassed 13dB boost 10 = 20dB boost 11 = 29dB boost Right Channel Input Select ...
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... WM8988 MONO MIXING The stereo ADC can operate as a stereo or mono device, or the two channels can be mixed to mono, either in the analogue domain (i.e. before the ADC the digital domain (after the ADC). MONOMIX selects the mode of operation. For analogue mono mix either the left or right channel ADC can be used, allowing the unused ADC to be powered off or used for a dc measurement conversion ...
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... RZCEN 0 5:0 RINVOL 010111 [5:0] ( 0dB ) 0 TOEN 0 WM8988 DESCRIPTION Left Volume Update 0 = Store LINVOL in intermediate latch (no gain change Update left and right channel gains (left = LINVOL, right = intermediate latch) Left Channel Input Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: LIVU must be set to un-mute. ...
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... WM8988 ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8988 uses a multi-bit, oversampled sigma-delta ADC for each channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1 ...
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... LAVU 0 7:0 RADCVOL 11000011 [7:0] ( 0dB ) 8 RAVU 0 WM8988 DESCRIPTION Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -97dB 0000 0010 = -96.5dB ... 0.5dB steps up to 1111 1111 = +30dB Left ADC Volume Update 0 = Store LADCVOL in intermediate latch (no gain change Update left and right channel ...
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... WM8988 AUTOMATIC LEVEL CONTROL (ALC) The WM8988 has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary ...
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... ALC attack (gain ramp-down) time [3:0] (24ms) 0000 = 6ms 0001 = 12ms 0010 = 24ms … (time doubles with every step) 1010 or higher = 6.14s WM8988 DESCRIPTION Note: ensure that LINVOL and RINVOL settings (reg. 0 and 1) are the same before entering this mode. PD, Rev 4.0, October 2008 23 ...
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... When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8988 has a noise gate function that prevents noise pumping by comparing the signal level at the LINPUT1/2 and/or RINPUT1/2 pins against a noise gate threshold, NGTH. The noise gate cuts in when: • ...
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... Switching the 3D filter from record to playback or from playback to record may only be done when ADC and DAC are disabled. The WM8988 control interface will only allow MODE3D to be changed when ADC and DAC are disabled (i.e. bits ADCL, ADCR, DACL and DACR in reg 1Ah are all zero) ...
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... The WM8988 output signal paths consist of digital filters, DACs, analogue mixers and output drivers. The digital filters and DACs are enabled when the WM8988 is in ‘playback only’ or ‘record and playback’ mode. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs) ...
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... Production Data GRAPHIC EQUALISER The WM8988 has a digital graphic equaliser and adaptive bass boost function. This function operates on digital audio data before it is passed to the audio DACs. Bass enhancement can take two different forms: • Linear bass control: bass signals are amplified or attenuated by a user programmable gain ...
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... CD with pre-emphasis used in the recording). De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. The WM8988 also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will return to the original setting. This function is enabled by default ...
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... Production Data OUTPUT MIXERS The WM8988 provides the option to mix the DAC output signal with analogue line-in signals from the LINPUT1/2, RINPUT1/2 pins or a mono differential input (LINPUT1 – RINPUT1) or (LINPUT2 – RINPUT2), selected by DS (see Table 6) . The level of the mixed-in signals can be controlled with PGAs (Programmable Gain Amplifiers) ...
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... WM8988 REGISTER ADDRESS R36 (24h) Right Mixer Control (1) R37 (25h) Right Mixer Control (2) Table 23 Right Output Mixer Control w BIT LABEL DEFAULT 8 LD2RO 0 7 LI2RO 0 6:4 LI2ROVOL 101 [2:0] (-9dB) 8 RD2RO 0 7 RI2RO 0 6:4 RI2ROVOL 101 [2:0] (-9dB) Production Data DESCRIPTION Left DAC to Right Mixer 0 = Disable (Mute) ...
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... RO1VU 0 7 RO1ZC 0 6:0 ROUT1VOL 1111001 [6:0] WM8988 DESCRIPTION Left Volume Update 0 = Store LOUT1VOL in intermediate latch (no gain change Update left and right channel gains (left = LOUT1VOL, right = intermediate latch) Left zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately LOUT1 Volume 1111111 = +6dB … ...
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... WM8988 REGISTER ADDRESS R24 (18h) HPCOM Control Table 25 HPCOM Control LOUT2/ROUT2 OUTPUTS The LOUT2 and ROUT2 output pins are essentially similar to LOUT1 and ROUT1, but they are independently controlled . REGISTER ADDRESS R40 (28h) LOUT2 Volume R41 (29h) ROUT2 Volume R24 (18h) ...
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... Production Data ENABLING THE OUTPUTS Each analogue output of the WM8988 can be separately enabled or disabled. The analogue mixer associated with each output is powered on or off along with the output pin. All outputs are disabled by default. To save power, unused outputs should remain disabled. ...
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... LRC: DAC and ADC data alignment clock • BCLK: Bit clock, for synchronisation The clock signals BCLK and LRC can be an output when the WM8988 operates as a master input when slave (see Master and Slave Mode Operation, below). Four different audio data formats are supported: • ...
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... Figure 14 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master) Figure 15 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master Justified Audio Interface (assuming n-bit word length) WM8988 st nd (mode (mode A) PD, Rev 4.0, October 2008 ...
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... WM8988 Figure 16 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave) Figure 17 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave) w Production Data PD, Rev 4.0, October 2008 36 ...
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... Tristates ADCDAT and switches ADCLRC, DACLRC and BCLK to inputs ADCDAT is an output, LRC and BCLK are inputs (slave mode) or outputs (master mode ADCDAT is tristated, LRC and BCLK are inputs WM8988 DESCRIPTION BCLK invert bit (for master and slave modes BCLK not inverted 1 = BCLK inverted ...
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... WM8988 MASTER MODE LRC ENABLE In Master mode the lrclk (LRC) is enabled by default only when the DAC is enabled. If ADC only operation in Master mode is required register bit LRCM must be set in oder to generate an lrclk. For DAC only operation LRCM may be set to ‘0’. REGISTER ...
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... Production Data CLOCKING AND SAMPLE RATES The WM8988 supports a wide range of master clock frequencies on the MCLK pin, and can generate many commonly used audio sample rates directly from the master clock. The ADC and DAC must always run at the same sample rate. ...
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... WM8988 MCLK MCLK ADC SAMPLE RATE CLKDIV2=0 CLKDIV2=1 ‘Normal’ Clock Mode (‘*’ indicates backward compatibility with WM8731) 8 kHz (MCLK/1536) 12.288 MHz 24.576 MHz 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 48 kHz (MCLK/256) 96 kHz (MCLK/128) 8.0182 kHz (MCLK/1408) 11.2896MHz 22.5792MHz 11 ...
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... SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8988 and the R/W bit is ‘0’, indicating a write, then the WM8988 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’, the WM8988 returns to the idle condition and wait for a new start condition and valid address ...
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... POWER MANAGEMENT The WM8988 has two control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To avoid any pop or click noise important to enable or disable functions in the correct order (see Applications Information). ...
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... Power down 1 = Power up 6 LOUT1 0 LOUT1 Output Buffer Power down 1 = Power up 5 ROUT1 0 ROUT1 Output Buffer Power down 1 = Power up 4 LOUT2 0 LOUT2 Output Buffer Power down 1 = Power up 3 ROUT2 0 ROUT2 Output Buffer Power down 1 = Power up WM8988 DESCRIPTION playback/record) standby) PD, Rev 4.0, October 2008 43 ...
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... WM8988 STOPPING THE MASTER CLOCK In order to minimise power consumed in the digital core of the WM8988, the master clock may be stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In Standby mode, setting DIGENB will typically provide an additional power saving on DCVDD of 20uA ...
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... Production Data SAVING POWER AT HIGHER SUPPLY VOLTAGES The analogue supplies to the WM8988 can run from 1.8V to 3.6V. By default, all analogue circuitry on the device is optimized to run at 3.3V. This set-up is also good for all other supply voltages down to 1.8V. At lower voltages, performance can be improved by increasing the bias current. If low power operation is preferred the bias current can be left at the default setting ...
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... WM8988 REGISTER MAP ADDRESS REGISTER remarks (Bit 15 – (00h) 0000000 Left Input volume R1 (01h) 0000001 Right Input volume R2 (02h) 0000010 LOUT1 volume R3 (03h) 0000011 ROUT1 volume R4 (04h) 0000100 Reserved R5 (05h) 0000101 ADC & DAC Control ADCDIV2 DACDIV2 R6 (06h) 0000110 Reserved ...
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... ADC FILTERS Mode 0 (250 USB) 1 (256/272) 2 (250 USB, 96k mode) 3 (256/272, 88.2/96k mode) WM8988 TYP MAX UNIT 0.416fs 0.5fs +/- 0. 0.4535fs 0.5fs +/- 0. 3.7 Hz 10.4 21.6 0.416fs 0.5fs +/-0. ...
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... WM8988 DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 21 DAC Digital Filter Frequency Response – Type 0 Figure 22 DAC Digital Filter Ripple – Type 0 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 23 DAC Digital Filter Frequency Response – Type 1 Figure 24 DAC Digital Filter Ripple – Type 1 ...
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... Frequency (Fs) Figure 31 ADC Digital Filter Frequency Response – Type 1 w 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0. 0.04 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0. Figure 30 ADC Digital Filter Ripple – Type 0 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 -0. 2.5 3 Figure 32 ADC Digital Filter Ripple – Type 1 0.05 0.1 0.15 0.2 Frequency (Fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (Fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (Fs) PD, Rev 4.0, October 2008 WM8988 0.25 0.45 0.5 0.45 0.5 49 ...
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... WM8988 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 33 ADC Digital Filter Frequency Response – Type 2 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 35 ADC Digital Filter Frequency Response – Type 2 DE-EMPHASIS FILTER RESPONSES -10 0 2000 4000 6000 8000 Frequency (Fs) Figure 37 De-emphasis Frequency Response (32kHz ...
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... Frequency (Fs) Figure 41 De-emphasis Frequency Response (48kHz) HIGHPASS FILTER The WM8988 has a selectable digital highpass filter in the ADC filter path to remove DC offsets. The filter response is characterised by the following polynomial -10 -15 0 0.0005 0.001 Frequency (Fs) Figure 43 ADC Highpass Filter Response w 0 ...
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... C10 Layout Notes C4, C17, C19, C20 and C21 should be as close to the relative WM8988 connecting pin as possible. 2. For capacitors C7 to C10, C14, C15, C22 and C23 it is recommended that low ESR components are used. 3. HPCOM and LCOM should be connected to GND at the connector. ...
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... RC filter, as high-frequency components in the input signal may otherwise cause aliasing distortion in the audio band. AC signals with no DC bias should be fed to the WM8988 through a DC blocking capacitor, e.g. 1µF. HEADPHONE OUTPUT CONFIGURATION Analogue outputs LOUT1/ROUT1 and LOUT2/ROUT2, can drive a 16Ω or 32Ω headphone load, as shown in Figure 45 ...
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... To minimize any pop or click noise when the system is powered up or down, the following procedures are recommended. POWER UP • Switch on power supplies. By default the WM8988 is in Standby Mode, the DAC is digitally muted and the Audio Interface, Line outputs and Headphone outputs are all OFF (DACMU = 1 Power Management registers 1 and 2 are all zeros). • ...
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... INDEX AREA (D/2 X E/2) SEE DETAIL aaa C aaa ccc C DETAIL 0.08 C 0.275MM A1 DETAIL DETAIL 2 MAX NOTE 0.600 0.05 1 0.28 4.05 4.05 5 DM050 TOP VIEW DETAIL 2 L PIN 1 IDENTIFICATION L1 Datum 0.150MM SQUARE Terminal Tip 0.275MM e PD, Rev 4.0, October 2008 WM8988 55 ...
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... WM8988 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...