wm8976gefl-v Wolfson Microelectronics plc, wm8976gefl-v Datasheet - Page 89

• Manufacturer Part Number: wm8976gefl-v
• Description: Stereo Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics plc

Production Data
w
5 (05h)
6 (06h)
REGISTER
ADDRESS
1
0
8:6
5
4:3
2:1
0
8
7:5
4:2
1
BIT
ADCLRSWAP
DACMONO
WL8
DAC_COMP
ADC_COMP
LOOPBACK
CLKSEL
MCLKDIV
BCLKDIV
LABEL
0
0
000
0
00
00
0
1
010
000
0
DEFAULT
Controls whether ADC data appears in ‘right’ or
‘left’ phases of LRC clock:
0=ADC data appear in ‘left’ phase of LRC
1=ADC data appears in ‘right’ phase of LRC
Selects between stereo and mono DAC operation:
0=Stereo device operation
1=Mono device operation. DAC data appears in
‘left’ phase of LRC
Reserved
Companding Control 8-bit mode
0=off
1=device operates in 8-bit mode
DAC companding
00=off (linear mode)
01=reserved
10=µ-law
11=A-law
ADC companding
00=off (linear mode)
01=reserved
10=µ-law
11=A-law
Digital loopback function
0=No loopback
1=Loopback enabled, ADC data output is fed
directly into DAC data input.
Controls the source of the clock for all internal
operation:
0=MCLK
1=PLL output
Sets the scaling for either the MCLK or PLL clock
output (under control of CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
Configures the BCLK output frequency, for use
when the chip is master over BCLK.
000=divide by 1 (BCLK=SYSCLK)
001=divide by 2 (BCLK=SYSCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
Reserved
DESCRIPTION
PD Rev 4.4 July 2009
Digital Audio
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REFER TO
WM8976
89