wm8953 Wolfson Microelectronics plc, wm8953 Datasheet
wm8953
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wm8953 Summary of contents
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... An integrated low power PLL provides support for most commonly-used audio sample rates. The WM8953 is supplied in very small and thin 42-ball WCSP package, ideal for portable systems. WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up ...
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... WM8953 DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 TABLE OF CONTENTS .........................................................................................2 BLOCK DIAGRAM .................................................................................................3 PIN CONFIGURATION...........................................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................6 RECOMMENDED OPERATING CONDITIONS .....................................................6 THERMAL PERFORMANCE .................................................................................7 ELECTRICAL CHARACTERISTICS ......................................................................8 TERMINOLOGY........................................................................................................... 12 TYPICAL POWER CONSUMPTION ....................................................................13 PSRR PERFORMANCE.......................................................................................14 AUDIO SIGNAL PATHS.......................................................................................15 SIGNAL TIMING REQUIREMENTS .....................................................................16 SYSTEM CLOCK TIMING............................................................................................ 16 AUDIO INTERFACE TIMING – MASTER MODE ......................................................... 17 AUDIO INTERFACE TIMING – ...
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... Production Data BLOCK DIAGRAM w WM8953 PD, January 2009, Rev 4.0 3 ...
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... WM8953 PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8953ECS/RV -40°C to +85°C Note: Reel quantity = 3500 w PACKAGE MOISTURE SENSITIVITY LEVEL 42-ball W-CSP MSL3 (Pb-free, Tape and reel) Production Data PEAK SOLDERING TEMPERATURE 260°C PD, January 2009, Rev 4.0 4 ...
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... Audio interface ADC left / right clock ADC digital audio data Selects 2-wire or 3/4 -wire control 3/4 -wire chip select or 2-wire address select Control interface clock input Control interface data input / 2-wire acknowledge output Midrail voltage decoupling capacitor GPIO pin GPIO pin GPIO pin WM8953 DESCRIPTION PD, January 2009, Rev 4.0 5 ...
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... WM8953 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process therefore generically susceptible to damage from excessive static voltages ...
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... Production Data THERMAL PERFORMANCE Thermal analysis should be performed in the intended application to prevent the WM8953 from exceeding maximum junction temperature. Several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device on the PCB in relation to surrounding components and the number of PCB layers. Connecting the GND balls through thermal vias and into a large ground plane will aid heat extraction ...
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... WM8953 ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = 3.3V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Analogue Input Pin Maximum Signal Levels (LIN1, LIN2, LIN3, LIN4, RIN1, RIN2, RIN3, RIN4) Maximum Full-Scale PGA Single-ended PGA Input Signal Level input on LIN1, LIN3, ...
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... Single PGA in differential mode, gain = -16.5dB PGA Outputs to INMIXL and INMIXR PGA Outputs to INMIXL and INMIXR PGA Outputs to INMIXL and INMIXR Line Inputs to INMIXL and INMIXR Line Inputs to INMIXL and INMIXR Line Inputs to INMIXL and INMIXR WM8953 MIN TYP MAX UNIT 57 kΩ ...
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... WM8953 Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = 3.3V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER ADC Input Path Performance SNR (A-weighted) Line inputs to ADC via INMIXL THD (-1dBFS input) and INMIXR, THD+N (-1dBFS input) AVDD = 3.3V Crosstalk (L/R) AVDD PSRR (217Hz) DCVDD PSRR (217Hz) ...
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... OPCLKDIV=1000 SYSCLK=PLL output; 45 OPCLKDIV=0000 SYSCLK=PLL output; 45 OPCLKDIV=1000 SYSCLK=MCLK; 33 OPCLKDIV=0100 SYSCLK=PLL output; 33 OPCLKDIV=0100 21 Input de-bounced SYSCLK 19 Input de-bounced SYSCLK TOCLKSEL=1 Input not de-bounced WM8953 TYP MAX UNIT AVDD/2 +3% V 0.9×AVDD +5% V 0.65×AVDD + 100 nV/√ 0.3×DBVDD V V 0.1×DBVDD V ...
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... WM8953 TERMINOLOGY 1. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum theoretical full scale output signal and the output with no input signal applied. 2. Total Harmonic Distortion (dB) – THD is the level of the rms value of the sum of harmonic distortion products relative to the amplitude of the measured output signal ...
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... No Clocks 3.3 3.3 3.6 3.6 2.7 1.8 3.0 2.5 No Clocks 3.3 3.3 3.6 3.6 2.7 1.8 3.0 2.5 With Clocks 3.3 3.3 3.6 3.6 2.7 1.8 3.0 2.5 fs=44.1kHz 3.3 3.3 3.6 3.6 2.7 1.8 3.0 2.5 fs=8kHz 3.3 3.3 3.6 3.6 WM8953 (V) (mA) (mA) (mA) (mW) 1.8 0.028 0.000 0.000 0.075 2.5 0.029 0.000 0.000 0.087 3.3 0.030 0.000 0.000 0.099 3.6 0.031 0.000 0.000 0.114 1.8 0.008 0.000 0.000 0.020 2.5 0.008 0.000 0.000 0.024 3.3 0.009 0.000 0.000 0.029 3.6 0.009 0.000 0.000 0.035 1 ...
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... WM8953 PSRR PERFORMANCE DCVDD – Line-In to ADC PSRR - DCVDD Line-In to ADC IN2-INMIX-ADC - 3.3V DCVDD 10 IN2-INMIX-ADC - 2.0V DCVDD 0 0.1 1 Frequency (kHz) AVDD – MICBIAS PSRR - AVDD MICBIAS MICBIAS - MBSEL = 0 10 MICBIAS - MBSEL = 1 0 0.1 1 Frequency (kHz) Note: All figures based on 100mVp-p injected on the supply at the relevant test frequency. ...
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... Production Data AUDIO SIGNAL PATHS w WM8953 PD, January 2009, Rev 4.0 15 ...
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... WM8953 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 2 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3V, DGND=AGND=0V, T PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle w t MCLKL t MCLKH t MCLKY SYMBOL CONDITIONS T MCLKY = T /T MCLKH MCLKL ...
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... PARAMETER Audio Data Timing Information ADCLRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge w o =+25 C, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless A SYMBOL MIN DDA WM8953 TYP MAX UNIT PD, January 2009, Rev 4.0 17 ...
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... WM8953 AUDIO INTERFACE TIMING – SLAVE MODE Figure 4 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3V, DGND=AGND=0V, T otherwise stated. PARAMETER Audio Data Input Timing Information BCLK cycle time BCLK pulse width high BCLK pulse width low ADCLRC set-up time to BCLK rising edge ...
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... In TDM mode important that two ADC devices to not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8953 ADCDAT tri-stating at the start and end of the data transmission is described in Figure 5 and the table below. Figure 5 Digital Audio Data Timing - TDM Mode Test Conditions AVDD=3 ...
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... WM8953 CONTROL INTERFACE TIMING – 2-WIRE MODE 2-wire mode is selected by connecting the MODE pin low. SDIN SCLK Figure 6 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3V, DGND=AGND=0V, T otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width ...
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... LSB =+25 C, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless A SYMBOL MIN t 40 CSU t 40 CHO t 200 SCY t 80 SCL t 80 SCH t 40 DSU t 10 DHO WM8953 TYP MAX UNIT PD, January 2009, Rev 4.0 21 ...
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... WM8953 CONTROL INTERFACE TIMING – 4-WIRE MODE 4-wire mode supports readback via SDOUT which is available as a GPIO pin function. Figure 9 Control Interface Timing – 4-Wire Serial Control Mode (Write Cycle) CSB SCLK SDOUT Figure 10 Control Interface Timing – 4-Wire Serial Control Mode (Read Cycle) Test Conditions DCVDD=1 ...
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... INTERNAL POWER ON RESET CIRCUIT Figure 11 Internal Power on Reset Circuit Schematic The WM8953 includes an internal Power-On-Reset Circuit, as shown in Figure 11, which is used to reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DCVDD. It asserts PORB low if AVDD or DCVDD is below a minimum threshold. ...
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... WM8953 Figure 13 Typical Power up Sequence where DCVDD is Powered before AVDD Figure 13 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that DCVDD is already up to specified operating voltage. When AVDD goes above the minimum threshold, V chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD rises ...
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... Production Data DEVICE DESCRIPTION INTRODUCTION The WM8953 is a low power, high quality audio ADC designed to interface with a wide range of processors and analogue components. A high level of mixed-signal integration in a very small 3.226x3.44mm footprint makes it ideal for portable applications such as mobile phones. Eight highly flexible analogue inputs allow interfacing four microphone inputs plus multiple stereo or mono line inputs (single-ended or differential) ...
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... The input paths are mixed together as illustrated in Figure 14. Figure 14 Control Registers for Input Signal Path MICROPHONE INPUTS Up to four microphones can be connected to the WM8953, either in single-ended or pseudo- differential mode. A low noise microphone bias is fully integrated to reduce the need for external components. ...
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... LIN4 and RIN4 should only be used as part of a differential line input with LIN3 and LIN4 four differential line inputs can be connected to LIN1+LIN2, LIN3+LIN4, RIN1+RIN2 and RIN3+RIN4. Figure 17 LIN1, RIN1, LIN3 or RIN3 as Line Inputs Figure 19 Differential Line Inputs w WM8953 Figure 16 Differential Microphone Input Figure 18 LIN2 or RIN2 as Line Inputs PD, January 2009, Rev 4.0 27 ...
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... Together with the external decoupling capacitor on VMID, the programmable resistor chain results in a slow, normal or fast charging characteristic on VMID. The VMID reference is controlled by VMID_MODE[1:0]. The analogue circuits in the WM8953 require a bias current. The bias current is enabled by setting VREF_ENA. Note that the bias current source requires VMID to be enabled also. REGISTER ...
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... After start-up, it may be desirable to disable an input stage, in order to reduce power consumption on an unused PGA or Input Mixer. In order to avoid audible pops caused by a disabling any part of the input circuits, the WM8953 can maintain the input at VMID even when the PGA or Input Mixer is disabled. This is achieved by connecting a buffered VMID reference to the input ...
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... WM8953 INPUT PGA CONFIGURATION Each of the four Input PGAs can be configured in single-ended or pseudo-differential mode. Single-ended microphone operation of an Input PGA is selected by connecting the input source to the inverting PGA input. The non-inverting PGA input must be connected to VMID by setting the appropriate register bits. ...
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... IPVU[2] N/A 7 RI12MUTE 1b 6 RI12ZC 0b WM8953 DESCRIPTION Input PGA Volume Update Writing this bit will cause all input PGA volumes to be updated simultaneously (LIN12, LIN34, RIN12 and RIN34) LIN12 PGA Mute 0 = Disable Mute 1 = Enable Mute LIN12 PGA Zero Cross Detector ...
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... WM8953 REGISTER ADDRESS R27 (1Bh) Table 7 Input PGA Volume Control w BIT LABEL DEFAULT 4:0 RIN12VOL 01011b [4:0] (0dB) 8 IPVU[3] N/A 7 RI34MUTE 1b 6 RI34ZC 0b 4:0 RIN34VOL 01011b [4:0] (0dB) Production Data DESCRIPTION RIN12 Volume (See Table 8 for volume range) Input PGA Volume Update Writing this bit will cause all input ...
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... Table 8 Input PGA Volume Range w VOLUME (DB) 00000 -16.5 00001 -15.0 00010 -13.5 00011 -12.0 00100 -10.5 00101 -9.0 00110 -7.5 00111 -6.0 01000 -4.5 01001 -3.0 01010 -1.5 01011 0 01100 +1.5 01101 +3.0 01110 +4.5 01111 +6.0 10000 +7.5 10001 +9.0 10010 +10.5 10011 +12.0 10100 +13.5 10101 +15.0 10110 +16.5 10111 +18.0 11000 +19.5 11001 +21.0 11010 +22.5 11011 +24.0 11100 +25.5 11101 +27.0 11110 +28.5 11111 +30.0 WM8953 PD, January 2009, Rev 4.0 33 ...
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... WM8953 INPUT MIXER ENABLE The WM8953 has two analogue input mixers which allow the Input PGAs and Line Inputs to be combined in a number of ways and output to the ADCs. The input mixers INMIXL and INMIXR are enabled by the AINL_ENA and AINR_ENA register bits, as described in Table 9 ...
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... RIN12 PGA Output to INMIXR Mute 0 = Mute 1 = Un-Mute 4 R12MNBST 0b RIN12 PGA Output to INMIXR Gain 0 = 0dB 1 = +30dB 8:6 RI2BVOL 000b RIN2 Pin to INMIXR Gain and Mute [2:0] (Mute) 000 = Mute 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB WM8953 DESCRIPTION PD, January 2009, Rev 4.0 35 ...
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... WM8953 ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8953 uses stereo 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC full scale input level is proportional to AVDD. See “Electrical Characteristics” for further details. Any input signal greater than full scale may overload the ADC and cause distortion ...
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... B9h 7Ah -26.250 BAh 7Bh -25.875 BBh 7Ch -25.500 BCh 7Dh -25.125 BDh 7Eh -24.750 BEh 7Fh -24.375 BFh WM8953 ADCL_VOL or Volume (dB) ADCR_VOL Volume (dB) -24.000 C0h 0.000 -23.625 C1h 0.375 -23.250 C2h 0.750 -22.875 C3h 1.125 -22.500 C4h 1.500 -22.125 C5h 1 ...
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... WM8953 HIGH PASS FILTER A digital high pass filter is applied by default to the ADC path to remove DC offsets. This filter can also be programmed to remove low frequency noise in voice applications (e.g. wind noise or mechanical vibration). This filter is controlled using the ADC_HPF_ENA and ADC_HPF_CUT register bits. In hi-fi mode the high pass filter is optimised for removing DC offsets without degrading the bass response and has a cut-off frequency of 3 ...
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... ADCs can be routed to either the left or the right channel of the digital audio interface. Independent functions enable either of the audio channels to be digitally inverted if required. See "Digital Audio Interface" for more information on the audio interface. Figure 20 shows the digital audio paths available in the WM8953 digital core. Figure 20 Digital Audio Paths w ...
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... Table 17 ADC Routing and Control THERMAL SENSING The WM8953 incorporates a thermal sensor in order to provide protection from overheating. The sensor is enabled by setting TSHUT_ENA. The status of the thermal sensor can be output on a GPIO pin and/or read from the GPIO registers. Alternatively, the temperature sensor can be configured to cause an Interrupt event. See “ ...
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... Production Data GENERAL PURPOSE INPUT/OUTPUT The WM8953 provides a number of versatile GPIO functions to enable features such as button and accessory detection and clock output. The WM8953 has five multi-purpose pins for these functions. • • The following functions are available on some or all of the GPIO pins. ...
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... WM8953 GPIO CONTROL REGISTERS Register bit AIF_TRIS, when set, tri-states all audio interface and GPIO pins. REGISTER ADDRESS R9 (09h) Table 20 GPIO and GPI Pin Function Select The GPIO pins are also controlled by the register fields described in Table 21. Note the order of precedence described earlier applies. ...
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... GPIn_ENA BIT LABEL DEFAULT 7:0 GPIO_POL 00h [7:0] (rw) WM8953 DESCRIPTION De-Bounce 0 = disabled (Not de-bounced enabled (Requires MCLK input and TOCLK_ENA = 1) IRQ Enable 0 = disabled 1 = enabled GPIO Pull-Up Resistor Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 150kΩ) GPIO Pull-Down Resistor Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 150kΩ ...
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... WM8953 BUTTON CONTROL The WM8953 GPIO supports button control detection with full status readback for up to four inputs (and one IRQ output). All inputs are latched at the IRQ Register, with de-bounce available for normal operation. De-bouncing may be disabled in order to allow the device to respond to wake-up events while the processor is disabled and is unable to provide a clock for de-bouncing ...
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... The MICBIAS current threshold status bits contained in the IRQ Register (R18) may be read at any time or else in response to an Interrupt event. See Table 30 for more details of the Interrupt function. If direct output of the MICBIAS current detect function is required to the external pins of the WM8953, the following register settings are required: • • ...
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... SYSCLK is derived from MCLK (either directly conjunction with the PLL), and is used to provide all internal clocking for the WM8953 (see "Clocking and Sample Rates" section for more information). A programmable clock divider OPCLKDIV controls the frequency of the OPCLK output. This clock is enabled by register bit OPCLK_ENA. See “ ...
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... TEMPOK_IRQ_ENA. The Temperature status bit contained in the IRQ Register (R18) may be read at any time or else in response to an Interrupt event. See Table 30 for more details of the Interrupt function. If direct output of the Temperature status bit is required to the external pins of the WM8953, the following register settings are required: • ...
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... PLL_LCK_IRQ_ENA. The PLL Lock status bit in the IRQ Register (R18) may be read at any time or else in response to an Interrupt event. See Table 30 for more details of the Interrupt function. If direct output of the PLL Lock status bit is required to the external pins of the WM8953, the following register settings are required: • ...
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... The IRQ bit cannot be reset the OR’d combination of all other registers and will reset only if R18[11:0] are all 0. If direct output of the Interrupt signal is required to external pins of the WM8953, the following register settings are required: • ...
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... WM8953 The IRQ register (R18) is described in Table 30. REGISTER ADDRESS R18 (12h) R23 (17h) GPIO Control (2) Table 30 GPIO Interrupt and Status Readback w BIT LABEL DEFAULT 12 IRQ Read Only (ro) 11 TEMPOK Read or Reset (rr) 10 MICSHRT Read or Reset (rr) 9 MICDET Read or Reset (rr) 8 PLL_LCK ...
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... GPIOn_PU = 0 for the selected SDOUT output pin GPIOn_PD = 0 for the selected SDOUT output pin BIT LABEL DEFAULT 15 RD_3W_ENA 1b 14 MODE_3W4W 0b WM8953 DESCRIPTION 3- / 4-wire readback configuration 1 = 3-wire mode 0 = 4-wire mode, using GPIO pin 3-wire mode 0 = push 0 open-drain 4-wire mode 0 = push 0 wired-OR PD, January 2009, Rev 4.0 ...
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... WM8953 GPIO SUMMARY The GPIO functions are summarised in Figure 22. Figure 22 GPIO Control Diagram w Production Data MCLK PD, January 2009, Rev 4.0 52 ...
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... Three typical scenarios are presented in the following Figure 25, Figure 26 and Figure 27. The examples are: • • • w Latch a GPIO input (Figure 25) Debounce and latch a GPIO input (Figure 26) Use the GPIOn_POL bit to implement an IRQ edge detect function (Figure 27) WM8953 PD, January 2009, Rev 4.0 53 ...
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... WM8953 The GPIO input or internal Interrupt event (eg. MICBIAS current detect) is latched as illustrated below: Figure 25 GPIO Latch The de-bounce function on the GPIO input pins enables transient behaviour to be filtered as illustrated below: Figure 26 GPIO De-bounce To implement an edge detect function on a GPIO input, the GPIOn_POL bits may be used to alternate the GPIO polarity after each edge transition ...
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... Production Data GPIO IRQ HANDLING In the following diagram Figure 28 a typical IRQ scenario is illustrated. Figure 28 GPIO IRQ Handling w WM8953 PD, January 2009, Rev 4.0 55 ...
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... PCM operation is supported using the DSP mode. MASTER AND SLAVE MODE OPERATION The WM8953 digital audio interface can operate as a master or slave as shown in Figure 29 and Figure 30. Figure 29 Master Mode The dual Audio Interface approach of the WM8953 has been implemented in such a way that it gives the user and application as much flexibility as possible ...
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... Time division multiplexing (TDM) allows multiple devices to transfer data simultaneously on the same bus. The WM8953 supports TDM in master and slave modes for all data formats and word lengths. TDM is enabled using register bit AIFADC_TDM. The TDM data slot is programmed using register bit AIFADC_TDM_CHAN ...
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... Figure 32 TDM with WM8953 as Master Figure 34 TDM with Processor as Master Note: The WM8953 is a 24-bit device. If the user operates the WM8953 in 32-bit mode then the 8 LSBs are not driven therefore recommended to add a pull-down resistor if necessary to the ADCDAT line in TDM mode. ...
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... The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. Figure 37 I2S Justified Audio Interface (assuming n-bit word length) w WM8953 PD, January 2009, Rev 4.0 59 ...
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... WM8953 In DSP mode, the left channel MSB is available on either the 1 edge of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of ADCLRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample ...
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... Production Data Figure 41 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave) PCM operation is supported in DSP interface mode. WM8953 ADC data that is output on the Left Channel will be read as mono PCM data by the receiving equipment. AUDIO DATA FORMATS (TDM MODE) TDM is supported in master and slave mode and is enabled by register bit AIF_ADC_TDM. All audio interface data formats support time division multiplexing (TDM) ...
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... WM8953 Figure 43 TDM in Left-Justified Mode ADCLRC BCLK ADCDAT Figure 44 TDM in I Figure 45 TDM in DSP Mode A ADCLRC BCLK ADCDAT Figure 46 TDM in DSP Mode B w 1/fs LEFT CHANNEL 1 BCLK 1 BCLK SLOT 0 SLOT Mode 1/fs 1 BCLK SLOT 0 LEFT SLOT 0 RIGHT SLOT 1 LEFT SLOT 1 RIGHT Production Data ...
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... AIF_TRIS 0 Audio Interface and GPIO Tristate 0 = Audio interface and GPIO pins operate normally 1 = Tristate all audio interface and GPIO pins WM8953 DESCRIPTION Left ADC Data Source Select 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel Right ADC Data Source Select ...
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... WM8953 MASTER MODE BCLK AND ADCLRC ENABLE The audio interface pins BCLK, ADCLRC and ADCDAT can be independently programmed to operate in master mode or slave mode using register bit AIF_MSTR. When the audio interface is operating in slave mode, the BCLK and ADCLRC clock outputs to these pins are by default disabled to allow the digital audio source to drive these pins ...
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... Production Data COMPANDING The WM8953 supports A-law and µ-law companding. This is selected as shown in Table 36. REGISTER ADDRESS R5 (05h) Table 36 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: µ-law (where µ=255 for the U.S. and Japan): F( µ ...
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... WM8953 Figure 48 µ-Law Companding 120 100 Figure 49 A-Law Companding w u-law Companding 120 100 0.1 0.2 0.3 0.4 Normalised Input A-law Companding 0.2 0.4 Normalised Input 0.5 0.6 0.7 0.8 0.9 1 0.6 0.8 1 PD, January 2009, Rev 4.0 Production Data 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 ...
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... This clock is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE. Table 38 to Table 43 show the clocking and sample rate controls for MCLK input, BCLK output (in master mode), ADCs, and GPIO clock output. The overall clocking scheme for the WM8953 is illustrated in Figure 50. PRESCALE MCLK_INV f ...
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... SYSCLK CONTROL MCLK may be inverted by setting register bit MCLK_INV. Note that it is not recommended to change the control bit MCLK_INV while the WM8953 is processing data as this may lead to clock glitches and signal pop and clicks. The SYSCLK_SRC bit is used to select the source for SYSCLK. The source may be either MCLK or the PLL output ...
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... Table 39 ADC Sample Rate Control w BIT LABEL DEFAULT 7:5 ADC_CLKDIV 000b [2:0] 10 AIF_LRCLKRAT 0b E WM8953 DESCRIPTION ADC Sample Rate Divider 000 = SYSCLK / 1.0 001 = SYSCLK / 1.5 010 = SYSCLK / 2.0 011 = SYSCLK / 3.0 100 = SYSCLK / 4.0 101 = SYSCLK / 5.5 110 = SYSCLK / 6.0 111= Reserved LRCLK Rate 0 = Normal mode (256 * fs USB mode (272 * fs) PD, January 2009, Rev 4 ...
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... WM8953 Table 40 ADC Sample Rates w SYSCLK ADC SAMPLE RATE DIVIDER 000 = SYSCLK / 1 001 = SYSCLK / 1.5 010 = SYSCLK / 2 011 = SYSCLK / 3 12.288 MHz 100 = SYSCLK / 4 101 = SYSCLK / 5.5 110 = SYSCLK / 6 111 = Reserved 000 = SYSCLK / 1 001 = SYSCLK / 1.5 010 = SYSCLK / 2 011 = SYSCLK / 3 11.2896 MHz 100 = SYSCLK / 4 101 = SYSCLK / 5.5 ...
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... BCLK_DIV 0100b [3:0] BIT LABEL DEFAULT 12:9 OPCLKDIV 0000b [3:0] 11 OPCLK_ENA 0b (rw) WM8953 DESCRIPTION BCLK Frequency (Master Mode) 0000 = SYSCLK 0001 = SYSCLK / 1.5 0010 = SYSCLK / 2 0011 = SYSCLK / 3 0100 = SYSCLK / 4 0101 = SYSCLK / 5.5 0110 = SYSCLK / 6 0111 = SYSCLK / 8 1000 = SYSCLK / 11 1001 = SYSCLK / 12 1010 = SYSCLK / 16 1011 = SYSCLK / 22 1100 = SYSCLK / 24 ...
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... WM8953 TOCLK CONTROL A slow clock (TOCLK) is derived from SYSCLK to enable input de-bouncing and volume update timeout functions. This clock is enabled by register bit TOCLK_ENA, and its frequency is controlled by TOCLK_RATE, as described in Table 43. REGISTER ADDRESS R6 (06h) Table 43 TOCLK Control USB MODE It is possible to reduce power consumption by disabling the PLL in some applications. One such application is when SYSCLK is generated from a 12MHz USB clock source. Setting the AIF_LRCLKRATE bit as described earlier (see “ ...
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... Production Data PLL The integrated PLL can be used to generate SYSCLK for the WM8953 from a wide range of MCLK reference frequencies. The PLL is enabled by the PLL_ENA register bit. If required, the input reference clock can be divided setting the register bit PRESCALE. The PLL frequency ratio R is equal register fields PLLN and PLLK, where PLLN is an integer (LSB = 1) and PLLK is the fractional portion of the number (MSB = 0 ...
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... WM8953 EXAMPLE PLL CALCULATION To generate 12.288MHz SYSCLK from a 12MHz reference clock: There is a fixed divide the PLL output (see Figure 50) followed by a selectable divide the same path. PLL output f (MCLK_DIV = 10b) sets the required f There is a selectable pre-scale (divide MCLK the PLL input (f ...
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... The remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register. Many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 8-bit address of each register in the WM8953). The default device address is 0011010 (0x34h). ...
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... Figure 52 2-Wire Serial Control Interface (single read) Figure 53 2-Wire Serial Control Interface (multiple write using auto-increment) Figure 54 2-Wire Serial Control Interface (multiple read using auto-increment) In 2-wire mode, the WM8953 has two possible device addresses, which can be selected using the CSB/ADDR pin. CSB/ADDR STATE ...
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... Production Data 3-WIRE / 4-WIRE SERIAL CONTROL MODES The WM8953 is controlled by writing to registers through 4-wire serial control interface. A control word consists of 24 bits. The first bit is the read/write bit (R/W), which is followed by 7 address bits (A6 to A0) that determine which control register is accessed. The remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register ...
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... WM8953 CSB SCLK R/W SDIN SDOUT control register address Figure 56 4-Wire Readback (Push 0/1) CSB SCLK SDIN R/W undriven SDOUT control register address Figure 57 4-Wire Readback (wired-OR B15 B14 B13 B12 B11 B10 B15 B14 B13 B12 B11 ...
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... Production Data POWER MANAGEMENT POWER MANAGEMENT REGISTERS The WM8953 has two control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To minimise pop or click noise important to enable or disable functions in the correct order. ...
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... WM8953 CHIP RESET AND ID The device ID can be read back from register 0. Writing to this register will reset the device. REGISTER ADDRESS R0 (00h) Reset / ID Table 52 Chip Reset and ID w BIT LABEL DEFAULT 15:0 SW_RESET_C 8990h HIP_ID [15:0] (rr) Production Data DESCRIPTION Writing to this register resets all registers to their default state ...
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... Production Data POWER DOMAINS Figure 58 WM8953 Power Domains w WM8953 PD, January 2009, Rev 4.0 81 ...
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... WM8953 REGISTER MAP w Production Data PD, January 2009, Rev 4.0 82 ...
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... Production Data Note: A bin default value of ‘p’ indicates a register field where a default value is not applicable e.g. a volume update bit. w WM8953 PD, January 2009, Rev 4.0 83 ...
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... WM8953 REGISTER BITS BY ADDRESS REGISTER BIT LABEL ADDRESS R0 (00h) 15:0 SW_RESET_CHIP_ ID Reset / ID [15:0] (rr) R1 (01h) 15:8 Power 7:5 Management 4 MICBIAS_ENA (1) (rw) 3 2:1 VMID_MODE [1:0] (rw) 0 VREF_ENA (rw) R02 (02h) 15 PLL_ENA Power (rw) Management (2) 14 TSHUT_ENA (rw) 13:12 11 OPCLK_ENA (rw AINL_ENA (rw) 8 AINR_ENA (rw) 7 LIN34_ENA (rw) 6 LIN12_ENA (rw) 5 RIN34_ENA (rw) 4 RIN12_ENA ...
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... Digital Audio Interface Format 00 = Right justified 01 = Left justified Format 11 = DSP Mode 0b Reserved - Do Not Change 40h Reserved - Do Not Change 00000b Reserved - Do Not Change 0b ADC Companding Enable 0 = disabled 1 = enabled 0b ADC Companding Type 0 = µ-law 1 = A-law 0b Reserved - Do Not Change WM8953 PD, January 2009, Rev 4.0 85 ...
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... WM8953 REGISTER BIT LABEL ADDRESS R06 (06h) 15 TOCLK_RATE Clocking (1) 14 TOCLK_ENA 13 12:9 OPCLKDIV [3:0] 8:5 4:1 BCLK_DIV [3:0] 0 R07 (07h) 15 Clocking (2) 14 SYSCLK_SRC 13 CLK_FORCE w DEFAULT DESCRIPTION 0b Timeout Clock Rate (Selects clock to be used for volume update timeout and GPIO input de-bounce SYSCLK / 2 (Slower Response SYSCLK / 2 ...
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... USB mode (272 * fs) 00b Reserved - Do Not Change 04h Reserved - Do Not Change 0060h Reserved - Do Not Change 0060h Reserved - Do Not Change 0000h Reserved - Do Not Change 00h Reserved - Do Not Change 1b ADC Digital High Pass Filter Enable 0 = disabled 1 = enabled 0b Reserved - Do Not Change WM8953 PD, January 2009, Rev 4.0 87 ...
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... WM8953 REGISTER BIT LABEL ADDRESS 6:5 ADC_HPF_CUT [1:0] 4:2 1 ADCL_DATINV 0 ADCR_DATINV R15 (0Fh) 15:9 Left ADC 8 ADC_VU Digital Volume 7:0 ADCL_VOL [7:0] R16 (10h) 15:9 Right ADC 8 ADC_VU Digital Volume 7:0 ADCR_VOL [7:0] R17 (11h) 15:0 R18 (12h) 15:13 GPIO Control 12 IRQ (1) (ro) 11 TEMPOK (rr) 10 MICSHRT (rr) 9 MICDET (rr) w DEFAULT DESCRIPTION 00b ...
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... MCLK input and TOCLK_ENA=1) 0b GPIO3 IRQ Enable 0 = disabled 1 = enabled (GPIO3 input will generate IRQ) 0b GPIO3 Pull-Up Resistor Enable 0 = Pull-up disabled 1 = Pull-up enabled (Approx 150kΩ) 1b GPIO3 Pull-Down Resistor Enable 0 = Pull-down disabled 1 = Pull-down enabled (Approx 150kΩ) WM8953 PD, January 2009, Rev 4.0 89 ...
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... WM8953 REGISTER BIT LABEL ADDRESS 3:0 GPIO3_SEL [3:0] R21 (15h) 15:8 GPIO5 7 GPIO5_DEB_ENA 6 GPIO5_IRQ_ENA 5 GPIO5_PU 4 GPIO5_PD 3:0 GPIO5_SEL [3:0] R22 (16h) 15 RD_3W_ENA GPI7 and GPI8 14 MODE_3W4W 13:12 11 TEMPOK_IRQ_ENA 10 MICSHRT_IRQ_EN A w DEFAULT DESCRIPTION 0000b GPIO3 Function Select 0000 = Input pin 0001 = Clock output (f=SYSCLK/OPCLKDIV) 0010 = Logic '0' 0011 = Logic '1' ...
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... Inverted 0b PLL Lock Polarity 0 = Non-inverted 1 = Inverted 00h GPIOn Input Polarity 0 = Non-inverted 1 = Inverted GPIO_POL[7]: GPI8 polarity GPIO_POL[6]: GPI7 polarity GPIO_POL[5]: Reserved GPIO_POL[4]: GPIO5 polarity GPIO_POL[3]: GPIO4 polarity GPIO_POL[2]: GPIO3 polarity GPIO_POL[1]: Reserved GPIO_POL[0]: Reserved 00h Reserved - Do Not Change WM8953 PD, January 2009, Rev 4.0 91 ...
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... WM8953 REGISTER BIT LABEL ADDRESS LIN12 Input 8 IPVU[0] PGA Volume 7 LI12MUTE 6 LI12ZC 5 4:0 LIN12VOL [4:0] R25 (19h) 15:9 LIN34 Input 8 IPVU[1] PGA Volume 7 LI34MUTE 6 LI34ZC 5 4:0 LIN34VOL [4:0] R26 (1Ah) 15:9 RIN12 Input 8 IPVU[2] PGA Volume 7 RI12MUTE 6 RI12ZC 5 4:0 RIN12VOL [4:0] R27 (1Bh) 15:9 RIN34 Input 8 IPVU[3] PGA Volume 7 RI34MUTE ...
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... Reserved - Do Not Change 0b LIN34 PGA Output to INMIXL Mute 0 = Mute 1 = Un-Mute 0b LIN34 PGA Output to INMIXL Gain 0 = 0dB 1 = +30dB 0b Reserved - Do Not Change 0b LIN12 PGA Output to INMIXL Mute 0 = Mute 1 = Un-Mute 0b LIN12 PGA Output to INMIXL Gain 0 = 0dB 1 = +30dB 0h Reserved - Do Not Change WM8953 PD, January 2009, Rev 4.0 93 ...
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... WM8953 REGISTER BIT LABEL ADDRESS R42 (2Ah) 15:9 Input Mixers 8 R34MNB (4) 7 R34MNBST 6 5 R12MNB 4 R12MNBST 3:0 R43 (2Bh) 15:9 Input Mixers 8:6 LI2BVOL (5) [2:0] 5:0 R44 (2Ch) 15:9 Input Mixers 8:6 RI2BVOL (6) [2:0] 5:0 R45 (2Dh) 15:0 R46 (2Eh) 15:0 R47 (2Fh) 15:0 R48 (30h) 15:0 R49 (31h) 15:0 R50 (32h) 15:0 R51 (33h) 15:0 R52 (34h) ...
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... Use values greater than 5 and less than 13. 00h Reserved - Do Not Change 31h Fractional (K) part of PLL frequency ratio (Most significant bits) 00h Reserved - Do Not Change 26h Fractional (K) part of PLL frequency ratio (Least significant bits) 0000h Reserved - Do Not Change 0b Extended Register Map Access 0 = disabled 1 = enabled WM8953 PD, January 2009, Rev 4.0 95 ...
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... WM8953 REGISTER BIT LABEL ADDRESS 0 R118 (76h) to Reserved R121 (79h) R122 (7Ah) 15 ADCL_ADCR_LINK Extended ADC Control 14:0 R123 (7Bh) to Reserved R127 (7Fh) w DEFAULT DESCRIPTION 0b Reserved - Do Not Change ADC Sync disabled 1 = ADC Sync enabled 2003h Reserved - Do Not Change Production Data PD, January 2009, Rev 4.0 ...
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... MAGNITUDE(dB) hpf_response2.res#1 MAGNITUDE(dB) Figure 62 ADC Digital High Pass Filter Ripple (48kHz, Voice Mode, ADC_HPF_CUT=01, 10 and 11) WM8953 TYP MAX UNIT 0.454 fs 0.5fs +/- 0. 18/fs 0.25 Frequency (fs) 12.624 31.716 79.683 200.19 502.96 1 ...
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... Wolfson recommend using a single, common ground reference. Where this is not possible care should be taken to optimise split ground configuration for audio performance. 2. Supply decoupling capacitors on DCVDD, DBVDD and AVDD should be positioned as close to the WM8953 as possible. Values indicated are minimum requirements. 3. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance. ...
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... THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 7. FOLLOWS JEDEC DESIGN GUIDE MO-211-C. w 3.440 0.7mm BODY, 0.50 mm BALL PITCH X X DETAIL CORNER 0. 0.10 D1 DETAIL 2 MAX NOTE 0.785 0.275 0.405 5 0.105 DM049 TOP VIEW Z f SOLDER BALL f h PD, January 2009, Rev 4.0 WM8953 E 99 ...
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... WM8953 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...