mtc20136pq STMicroelectronics, mtc20136pq Datasheet - Page 19

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mtc20136pq

Manufacturer Part Number
mtc20136pq
Description
Adsl Transceiver Controller
Manufacturer
STMicroelectronics
Datasheet

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Generic Parallel Interface
The two parallel bus modes differ only in the definition of 3 control signals: busmode 0 provides a read/
write selector, a data strobe and a ready acknowledge. Busmode 1 provides a read strobe, a write strobe
and a ready acknowledge. The signal definition is shown in following table:
Table 7. Ctrl-E interface signals in parallel interface modes
Write cycle timing
Figure 8. Ctrl-E interface: write cycle timing in parallel modes 0 and 1
Mode 0 : Motorola-compatible mode
Mode 1 : Intel-compatible mode
C_Rd/notWr
C_notDtAck
Signal name
C_Mode[1:0]
C_Mode[1:0]
C_Rd/notWr
C_notDtAck
C_D[7:0]
C_A[8:0]
C_notRdy
C_notDS
C_notWr
C_notCS
C_notRd
C_notRdy
C_notCS
C_notDS
C_A[8:0]
C_D[7:0]
C_notWr
C_notRd
C_notInt
t1
Type
OZ
OZ
OZ
IO
t2
I
I
I
I
I
I
I
I
t6
address bus
byte wide bidirectional data bus
chip select
Interrupt output, derived from CtrleInt1 signal from
Mailbox : low when CtrleInt1 is low, else tri-stated
00
read access if 1, write access if 0
Data Strobe
Bus cycle ready indication, indicates that data on bus
can be sampled or removed
01
write cycle indication
read cycle indication
Bus cycle ready indication, indicates that data on bus
can be sampled or removed, same as in mode 0
b
b
t3
t4
t7
t8
t5
Function
t9
C_Mode[1:0]
C_Mode[1:0]
C_notRdy
C_notRdy
C_notCS
C_A[8:0]
C_D[7:0]
C_notWr
C_notRd
C_notWr
C_notRd
C_notInt
MTC20136
PIN
Mode 0
Mode 1
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