ICS9112 Integrated Circuit System, ICS9112 Datasheet - Page 5

• Manufacturer Part Number: ICS9112
• Description: Zerodelay, 3.3V Tolerant W/CLKOUT, hi BW
• Manufacturer: Integrated Circuit System

Output to Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the
inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase
difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded than
CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause them to
have different rise times and different times crossing the measurement thresholds.
REF input and CLK(1-4)
outputs loaded equally, with
CLKOUT loaded More.
Timing diagrams with different loading configurations
5
REF input and
all outputs
loaded Equally
REF input and CLK(1_4)
outputs loaded equally, with
CLKOUT loaded Less.
ICS9112-16