ICS9112 Integrated Circuit System, ICS9112 Datasheet

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ICS9112

Manufacturer Part Number
ICS9112
Description
Zerodelay, 3.3V Tolerant W/CLKOUT, hi BW
Manufacturer
Integrated Circuit System
Datasheet

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General Description
Block Diagram
Low Skew Output Buffer
The ICS9112-16 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the REF input with the
CLKOUT signal. It is designed to distribute high speed
clocks in PC systems operating at speeds from 25 to
133 MHz.
ICS9112-16 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to the
input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
The ICS9112-16 comes in an eight pin 150 mil SOIC or 173
mil TSSOP package. It has five output clocks. In the absence
of REF input, will be in the power down mode. In this mode,
the PLL is turned off and the output buffers are pulled low.
Power down mode provides the lowest power consumption
for a standby condition.
9112-16 Rev G 02/06/02
Features
Zero input - output delay
Frequency range 25 - 133 MHz (3.3V)
High loop filter bandwidth ideal for Spread
Spectrum applications.
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC
or 173 mil TSSOP package.
3.3V ±10% operation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Pin Configuration
8 pin SOIC, TSSOP
ICS9112-16

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ICS9112 Summary of contents

Page 1

... PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. The ICS9112-16 comes in an eight pin 150 mil SOIC or 173 mil TSSOP package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low ...

Page 2

... ICS9112-16 Pin Descriptions Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. ...

Page 3

... ICS9112-16 +0 ...

Page 4

... ICS9112-16 Switching Characteristics ...

Page 5

... REF input and CLK(1-4) outputs loaded equally, with CLKOUT loaded More. Timing diagrams with different loading configurations REF input and all outputs loaded Equally REF input and CLK(1_4) outputs loaded equally, with CLKOUT loaded Less. 5 ICS9112-16 ...

Page 6

... ICS9112-16 N INDEX INDEX AREA AREA 45° 45° Ordering Information ICS9112yM-16-T Example: ICS XXXX PPP - T C SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS VARIATIONS N SEATING SEATING PLANE PLANE 8 Reference Doc.: JEDEC Publication 95, MS-012 ...

Page 7

... Pattern Number ( digit number for parts with ROM code patterns) Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists digit numbers) Prefix ICS Standard Device 7 ICS9112-16 In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN -- 1 ...

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