ICS83940-01I Integrated Circuit System, ICS83940-01I Datasheet
![no-image](/images/no-image-200.jpg)
ICS83940-01I
Related parts for ICS83940-01I
ICS83940-01I Summary of contents
Page 1
... The effective fanout can be increased from utilizing the ability of the outputs to drive two series terminated lines. The ICS83940I-01 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes. Guar- anteed output and part-to-part skew characteristics make the ICS83940I-01 ideal for those clock distribution applications de- manding well defined performance and repeatability ...
Page 2
... " www.icst.com/products/hiperclocks.html 2 ICS83940I- KEW ANOUT ...
Page 3
... These ratings are stress specifications only. Functional + 0.3V operation of product at these conditions or any conditions be- DDO yond those listed in the DC Characteristics or AC Character- ±20mA istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. www.icst.com/products/hiperclocks.html 3 ICS83940I- -18 OW KEW TO B ANOUT UFFER REV ...
Page 4
... ICS83940I- KEW ANOUT ...
Page 5
... ICS83940I- KEW B ANOUT 85° ...
Page 6
... ICS83940I- KEW B ANOUT ...
Page 7
... GND = -1.25V±5% 3.3V/2.5V O UTPUT V DD SCOPE nPCLK PCLK GND D I IFFERENTIAL NPUT V DDO UTPUT KEW www.icst.com/products/hiperclocks.html 7 ICS83940I- KEW TO B ANOUT UFFER SCOPE OAD EST IRCUIT V Cross Points CMR L EVEL DDO 2 tsk(o) REV. A JANUARY 17, 2003 -18 ...
Page 8
... IME V DDO 2 Q0:Q17 Pulse Width t PERIOD t PW odc = t PERIOD odc & ERIOD 83940DYI-01 PRELIMINARY LVPECL- -LVCMOS / LVTTL F TO 1.8V 2.4V 0.5V 0.5V Clock Outputs UTPUT ISE www.icst.com/products/hiperclocks.html 8 ICS83940I- -18 OW KEW TO B ANOUT UFFER 2.4V 0. ALL IME REV. A JANUARY 17, 2003 ...
Page 9
... For example, if the input DD clock swing is only 2.5V and V and R2/R1 = 0.609. VDD R1 1K PCLK V_REF nPCLK C1 0. INGLE NDED IGNAL RIVING IFFERENTIAL www.icst.com/products/hiperclocks.html 9 ICS83940I- -18 OW KEW TO B ANOUT UFFER = 3.3V, V_REF should be 1.25V DD I NPUT REV. A JANUARY 17, 2003 ...
Page 10
... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS83940I-01 is: 819 83940DYI-01 PRELIMINARY LVPECL- -LVCMOS / LVTTL ...
Page 11
... ° www.icst.com/products/hiperclocks.html 11 ICS83940I- KEW TO B ANOUT UFFER ° REV. A JANUARY 17, 2003 ...
Page 12
... www.icst.com/products/hiperclocks.html 12 ICS83940I- KEW ANOUT ° ...