ICS83940-01 Integrated Circuit System, ICS83940-01 Datasheet

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ICS83940-01

Manufacturer Part Number
ICS83940-01
Description
Manufacturer
Integrated Circuit System
Datasheet
G
pair can accept LVPECL, CML or SSTL input levels. The single
ended clock input accepts LVCMOS or LVTTL input levels.
The low impedance LVCMOS/LVTTL outputs are designed to
drive 50 series or parallel terminated transmission lines. The
effective fanout can be increased from 18 to 36 by utilizing
the ability of the outputs to drive two series terminated lines.
The ICS83940-01 is characterized at full 3.3V, full 2.5V and mixed
3.3V input and 2.5V output operating supply modes. Guaran-
teed output and part-to-part skew characteristics make the
ICS83940-01 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
83940DY-01
B
HiPerClockS™
,&6
LVCMOS_CLK
ENERAL
LOCK
CLK_SEL
nPCLK
PCLK
The ICS83940-01 is a low skew, 1-to-18 LVPECL-
to-LVCMOS/LVTTL Fanout Buffer and a member
of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS83940-01 has
two selectable clock inputs. The PCLK, nPCLK
D
IAGRAM
D
ESCRIPTION
0
1
www.icst.com/products/hiperclocks.html
18
Q0:Q17
LVPECL-
1
P
F
18 LVCMOS/LVTTL outputs, 23 typical output impedance
Selectable LVCMOS_CLK or LVPECL clock inputs
LVCMOS_CLK supports the following input types:
LVCMOS or LVTTL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum output frequency: 250MHz
Output skew: 85ps (maximum)
Part-to-part skew: 750ps (maximum)
Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Pin compatible with the MPC940L in single supply
applications
IN
EATURES
LVCMOS_CLK
TO
A
CLK_SEL
-LVCMOS / LVTTL F
SSIGNMENT
nPCLK
PCLK
GND
GND
V
V
DDO
DD
7mm x 7mm x 1.4mm package body
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
ICS83940-01
32-Lead LQFP
Y Pacakge
Top View
L
ICS83940-01
OW
S
ANOUT
KEW
REV. A APRIL 11, 2003
24
23
22
21
20
19
18
17
, 1-
B
Q6
Q7
Q8
V
Q9
Q10
Q11
GND
TO
UFFER
DDO
-18

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ICS83940-01 Summary of contents

Page 1

... The effective fanout can be increased from utilizing the ability of the outputs to drive two series terminated lines. The ICS83940-01 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes. Guaran- teed output and part-to-part skew characteristics make the ICS83940-01 ideal for those clock distribution applications de- manding well defined performance and repeatability ...

Page 2

... " www.icst.com/products/hiperclocks.html 2 ICS83940- KEW ANOUT ...

Page 3

... These ratings are stress specifications only. Functional + 0.3V operation of product at these conditions or any conditions be- DDO yond those listed in the DC Characteristics or AC Character- ±20mA istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. www.icst.com/products/hiperclocks.html 3 ICS83940- -18 OW KEW TO B ANOUT UFFER REV ...

Page 4

... ICS83940- KEW ANOUT ...

Page 5

... ICS83940- KEW B ANOUT 70° ...

Page 6

... ICS83940- KEW B ANOUT ...

Page 7

... GND = -1.25V±5% 3.3V/2.5V O UTPUT V DD SCOPE nPCLK PCLK GND D I IFFERENTIAL NPUT V DDO UTPUT KEW www.icst.com/products/hiperclocks.html 7 ICS83940- KEW TO B ANOUT UFFER SCOPE OAD EST IRCUIT V Cross Points CMR L EVEL DDO 2 tsk(o) REV. A APRIL 11, 2003 -18 ...

Page 8

... ALL IME V DDO 2 LVCMOS_CLK nPCLK PCLK V DDO 2 Q0:Q17 ROPAGATION ELAY 83940DY-01 LVPECL- -LVCMOS / LVTTL F TO 80% Q0:Q17 20 odc & ERIOD www.icst.com/products/hiperclocks.html 8 ICS83940- -18 OW KEW TO B ANOUT UFFER V DDO 2 Pulse Width t PERIOD t PW odc = t PERIOD REV. A APRIL 11, 2003 ...

Page 9

... For example, if the input DD clock swing is only 2.5V and V and R2/R1 = 0.609. VDD R1 1K PCLK V_REF nPCLK C1 0. INGLE NDED IGNAL RIVING IFFERENTIAL www.icst.com/products/hiperclocks.html 9 ICS83940- -18 OW KEW TO B ANOUT UFFER = 3.3V, V_REF should be 1.25V DD I NPUT REV. A APRIL 11, 2003 ...

Page 10

... HiPerClockS Input 2D. H NPUT RIVEN IGURE 3. PCLK nPCLK HiPerClockS PCLK/nPCLK R2 125 D NPUT RIVEN AC C OUPLE www.icst.com/products/hiperclocks.html 10 ICS83940- KEW B ANOUT 2.5V 3. 120 120 Ohm PCLK Ohm nPCLK HiPerClockS PCLK/nPCLK R1 R2 120 120 PCLK/ ...

Page 11

... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS83940-01 is: 819 83940DY-01 LVPECL- -LVCMOS / LVTTL ...

Page 12

... ° www.icst.com/products/hiperclocks.html 12 ICS83940- KEW TO B ANOUT UFFER ° REV. A APRIL 11, 2003 ...

Page 13

... www.icst.com/products/hiperclocks.html 13 ICS83940- KEW B ANOUT ° ...

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