ICS83940 Integrated Circuit System, ICS83940 Datasheet - Page 7

• Manufacturer Part Number: ICS83940
• Manufacturer: Integrated Circuit System

W
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
T
T
The transistor count for ICS83940 is: 820
83940BY
ABLE
RANSISTOR
IRING THE
6.
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
JA
C
VS
D
OUNT
. A
IFFERENTIAL
IR
F
LOW
T
ABLE
I
F
NPUT TO
IGURE
q
1. S
JA
A
R
A
by Velocity (Linear Feet per Minute)
CLK_IN
PPLICATION
www.icst.com/products/hiperclocks.html
INGLE
CCEPT
ELIABILITY
0.1uF
C1
E
NDED
S
INGLE
DD
LVPECL-
/2 is
S
IGNAL
R1
1K
V_REF
R2
1K
E
7
I
I
NDED
NFORMATION
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
NFORMATION
D
V
RIVING
DD
+
-
L
67.8°C/W
47.9°C/W
TO
EVELS
D
-LVCMOS/LVTTL F
0
IFFERENTIAL
55.9°C/W
42.1°C/W
I
200
NPUT
DD
= 3.3V, V_REF should be 1.25V
L
OW
50.1°C/W
39.4°C/W
S
ICS83940
REV. A DECEMBER 12, 2002
500
ANOUT
KEW
, 1-
B
TO
UFFER
-18