pt7a4409 Pericom Technology Inc, pt7a4409 Datasheet - Page 8

• Manufacturer Part Number: pt7a4409
• Description: T1/e1/oc3 System Synchronizer
• Manufacturer: Pericom Technology Inc

| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
Whenever there is a change in the input reference source, such
as a switch from the primary reference signal (PRI) to second-
ary reference signal (SEC), the typical result is a step change in
phase of the DPLL input signal that causes an unacceptable
step change in the DPLL input signal phase. The TIE Corrector
circuit is used to eliminate the step change in the DPLL input
signal phase, thus maintaining continuity of phase at the DPLL
output.
Referring to Figure 3, the selected reference signal (e.g. SEC)
feeds the Comparing Circuit where it is compared with the feed-
back signal from the output circuit. Whenever there is a step
change in the reference input signal`s phase, the Comparing
Circuit will generates a Delay Value for the Programmable Delay
Circuit. The Delay Circuit then delays the input reference signal
by the Delay Value, thus providing the DPLL with a Virtual
Reference Signal having no phase discontinuity.
The DPLL phase detects and tracks the Virtual Reference Sig-
nal. As the Virtual Reference Signal exhibits no discontinuity of
phase, there is no phase transient in the DPLL output signal.
This is the Normal operation of the device
During the input reference signals source switching process, a
holdover state will occurr before the DPLL begins to track the
Virtual Reference Signal. When the input reference is switched
to the new source, the State Machine initiates Holdover State,
during which the DPLL does not use the Virtual Reference Sig-
nal. Instead, it uses stored information to produce a clock sig-
nal that is compared in the Comparing Circuit with the Feed-
back Signal. This compared result is sent to the Programmable
Delay Circuit which in turn delivers to the DPLL input a new
Virtual Reference Signal whose phase is aligned with that of the
previous input reference signal. The State Machine then termi-
nates Holdover State and return the device to Normal state.
PT0103(12/05)
Figure 4. Block Diagram of DPLL
Reference
from TIE
Corrector
Virtual
Frequency Select MUX
Feedback Signal
Detector
Phase
From
.
Limiter
State Select From
Input Impairment
Monitor
Control Circuit
8
As the Programmable Delay Circuit maintains the phase of the
Virtual Reference Signal while the TIE Corrector is enabled,
there will in general be a time delay between the chip output
signals and the selected input reference signal after switching
to a new input reference source (e.g. from PRI to SEC). Each
time a new reference source is selected, there will in general be
a new time delay. The value of this delay represents the accu-
mulation of the phase errors measured and corrected for during
the various reference source switching events.
The Programmable Delay Circuit can be zeroed through the
TCLR pin (low level, min. duration 300ns), realigning the output
signals with the present input reference signal. The speed of
realignments is limited by the Limiter in the DPLL to 5ns per
125µs. Convergence is in the direction of least phase travel.
Digital Phase-Locked Loop (DPLL)
The DPLL consists of the Phase Detector, Limiter, Loop Filter,
Digitally Controlled Oscillators (DCO1 and DCO2) and Control
Circuit. See Figure 4 for the block diagram of DPLL.
The Virtual Reference Signal from TIE is sent to Phase Detector
for comparison with the Feedback Signal from the Feedback
Frequency Select MUX. An error signal corresponding to their
instantaneous phase difference is produced and sent to the
Limiter.
sponds to all input transient conditions with a maximum output
phase slope of 5ns per 125µs. This performance easily
the maximum phase slope of 7.6ns per 125µs or 81ns per 1.326ms
specified by AT&T TR62411.
The Loop Filter is a 1.9Hz low pass filter for all three reference
frequency selections: 8kHz, 1.544MHz and 2.048MHz. The filter
ensures that the jitter transfer requirements in ETS 300-011 and
AT&T TR62411 are met.
he Limiter amplifies this error signal to ensure the DPLL re-
Filter
Loop
State Machine
State Select
T1/E1/OC3 System Synchronizer
From
DCO
PT7A4409/4409L
DPLL Reference
Output Interface
Data Sheet
Circuit
to
Ver:2