pt7a4409 Pericom Technology Inc, pt7a4409 Datasheet
pt7a4409
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pt7a4409 Summary of contents
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... ETS 300 011 in jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, holdover accuracy, capture range, phase slope and MTIE, etc. The PT7A4409/4409L operates in Manual or Automatic Mode, and in each of the modes, three operating states are available: Normal, Holdover and Free-Run. Ordering Information ...
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... Overall Operation .................................................................................................................................. 7 Modes and States of Operation ............................................................................................................ 10 Applications Information....................................................................................................................... 14 Detailed Specifications ................................................................................................................................ 16 Definitions of Critical Performance Specifictions .................................................................................... 16 Absolute Maximum Ratings .................................................................................................................. 18 Recommended Operating Conditions.................................................................................................... 18 DC Electrical and Power Supply Characteristics ................................................................................... 19 AC Electrical Characteristics ................................................................................................................ 20 Mechanical Specifications ........................................................................................................................... 33 Note .......................................................................................................................................................... 34 PT0103(12/05) T1/E1/OC3 System Synchronizer Contents 2 Data Sheet PT7A4409/4409L Ver:2 ...
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... GND TCLR CC Virtual Reference TIE DPLL Corrector State State Select Select Input Impairment Monitor Guard Time Circuit MS2 GTo GTi 3 Data Sheet PT7A4409/4409L ACKi APLL ACKo C1 Output C6 Interface C8 Circuit C16 C19 F0 F8 F16 RSP TSP Feedback Frequency Select MUX FS1 ...
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... PLCC Top View 4 Data Sheet PT7A4409/4409L ...
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... Data Sheet PT7A4409/4409L ...
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... Data Sheet PT7A4409/4409L ...
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... Referring to the block diagram on Page 3, the detailed functions of the PT7A4409/4409L are described as follows. Master Clock The PT7A4409/4409L uses either an external clock source or an external crystal and a few discrete components with its internal oscillator as the master clock. Reference Select MUX The PT7A4409/4409L accepts two independent reference sig- nals, the primary reference and secondary reference ...
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... The filter ensures that the jitter transfer requirements in ETS 300-011 and AT&T TR62411 are met. Loop Limiter Filter Control Circuit State Select From State Select Input Impairment From Monitor State Machine 8 Data Sheet PT7A4409/4409L DPLL Reference to DCO Output Interface Circuit Ver:2 ...
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... Tapped Delay Line in the Output Interface Circuit to produce 12.352MHz, 12.624MHz, 19.44MHz and 16.384MHz sig- nals. The DCO synchronization method depends upon the PT7A4409/4409L operating state, as follows: In Normal state, the DCO generates four output signals which are frequency and phase locked to the selected input reference signal ...
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... U.I.. the analog PLL has an intrinsic jitter level sepatate pins are provided to power (AVDD, AGND) the analog PLL. Modes and States of Operation The PT7A4409/4409L operates either in Manual mode or Auto- matic mode. Each mode has three possible operating states, Normal, Holdover or Free-Run. ...
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... Typically the Free-Run State is used when a master clock is required or immediately following system power-up before net- work synchronization is achieved. In Free-Run State, the outputs of the PT7A4409/4409L are uncorrelated with the input reference signal and the stored in- formation of output reference. Instead, these output signals are based solely on the master clock frequency (OSCi) ...
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... S2A S1A Auto-Holdover Secondary Primary (001) (000) S2H S1H Holdover Holdover Secondary Primary (011) (010) * Movement to Normal State from any state requires a valid input signal. 12 Data Sheet PT7A4409/4409L ...
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... Auto-Holdover Primary Secondary (X0X) (011) (X0X) (011) (010 or 11X) S2H S1H Holdover Holdover Secondary Primary * Movement to Normal State from any state requires a valid input signal. 13 Data Sheet PT7A4409/4409L ...
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... Applications Information Master Clock The PT7A4409/4409L uses either an external clock source or an external crystal as the master timing source. In Free-Run State, the frequency tolerance of the PT7A4409/ 4409L output clocks are equal to the frequency tolerance of the timing source ...
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... The timing diagram is shown in Figure 13. Figure 12. Unsymmetrical Guard Time Circuit PT7A4409/4409L GTo + C 10µF GTi Good Bad Good Bad PRI PRI PRI Holdover Normal Holdover 15 Data Sheet PT7A4409/4409L R C 150kΩ 10µ 1kΩ 1kΩ Good SEC PRI Normal Normal Ver:2 ...
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... C3 binations can be derived from them. 0.1µF For the PT7A4409/4409L, two internal elements determine the jitter attenuation. They are internal 1.9Hz low pass loop filter and phase slope limiter. The phase slope limiter limits the out- put phase slope to 5ns/125µs. Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i ...
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... Capture Range can fall outside the Lock Range, and, in general, the Capture Range is more narrow than the Lock Range. However, owing to the design of its Phase Detector, the PT7A4409/ 4409L`s Capture Range is equal to its Lock Range. Phase Slope: Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal of constant frequency ...
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... Data Sheet PT7A4409/4409L ...
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... and V measurement Data Sheet PT7A4409/4409L ...
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... Data Sheet PT7A4409/4409L * ...
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... Timing Reference Points 21 Data Sheet PT7A4409/4409L ...
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... Data Sheet PT7A4409/4409L ...
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... Data Sheet PT7A4409/4409L ...
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... Data Sheet PT7A4409/4409L ...
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... F16WL t C16WL t t C8W C8W t C4W t C4W t C2W t t C3W C3W t C15W t t C6W C6W t C19W t C19W t RSPD t TSPW t TSPD 25 Data Sheet PT7A4409/4409L t F8WH F0D C16D C8D C4D C2D C3D C15D C6D ...
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... Data Sheet PT7A4409/4409L ...
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... Data Sheet PT7A4409/4409L ...
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... Data Sheet PT7A4409/4409L ...
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... Data Sheet PT7A4409/4409L ...
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... Data Sheet PT7A4409/4409L ...
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... For Free-Run State of±100ppm. 18. For capture range of±230ppm. 19. For capture range of ±198ppm. 20. For capture range of ±130ppm. 21. 25pF capacitive load. PT0103(12/05) PT7A4409/4409L T1/E1/OC3 System Synchronizer 22. OSCi Master Clock Jitter is less than 2ns p-p, or 0.04UI p-p where 1UI p-p = 1/20MHz. 23. Jitter on reference input is less than 7ns p-p. 24. Applied jitter is sinusoidal. ...
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... Mechanical Specifications Figure 21. 44-pin PLCC PT0103(12/05) PT7A4409/4409L T1/E1/OC3 System Synchronizer 33 Data Sheet ...
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... Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0103(12/05) T1/E1/OC3 System Synchronizer Note Pericom Technology Inc. Web-Site: www.pti.com.cn, www.pti-ic.com Fax: (86)-21-6485 2181 Fax: (852)- 2243 3667 Fax: (1)-408-435 1100 34 Data Sheet PT7A4409/4409L Ver:2 ...