pt7a4402b Pericom Technology Inc, pt7a4402b Datasheet - Page 17

• Manufacturer Part Number: pt7a4402b
• Description: T1/e1 System Synchronizer
• Manufacturer: Pericom Technology Inc

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Using the above method, the jitter attenuation can be calcu-
lated for all combinations of inputs and outputs based on the
three jitter transfer functions provided.
Note that the resulting jitter transfer functions for all combina-
tions of inputs (8kHz, 1.544MHz, 2.048MHz) and outputs (8kHz,
1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz) for a
given input signal (jitter frequency and jitter amplitude) are the
same.
Since intrinsic jitter is always present, jitter attenuation will
appear to be lower for small input jitter signals than for large
ones. Consequently, accurate jitter transfer function measure-
ments are usually made with large input jitter signals (e.g., 75%
of the specified maximum jitter tolerance).
Frequency Accuracy: Frequency accuracy is defined as the
absolute tolerance of an output clock signal when it is not
locked to an external reference, but is operating in a free run-
ning mode. For the PT7A4402B/4402L, the Free-Run accuracy
is equal to the Master Clock (OSCi) accuracy.
Holdover Accuracy: Holdover accuracy is defined as the abso-
lute tolerance of an output clock signal, when it is not locked to
an external reference signal, but is operating using storage tech-
niques. For the PT7A4402B/4402L the storage value is deter-
mined while the device is in Normal State and locked to an
external reference signal. The absolute Master Clock (OSCi)
accuracy of the PT7A4402B/4402L does not affect Holdover
accuracy, but the change in OSCi accuracy while in Holdover
Mode does.
Lock Range: If the PT7A4402B/4402L DPLL is already in a
state of synchronization (lock) with the incoming reference
signal, it is able to track this signal to maintain lock as its fre-
quency varies over a certain range, called the Lock Range. The
size of Lock Range is related to the range of the Digitally Con-
trolled Oscillators and is equal to 230ppm minus the accuracy
of the master clock (OSCi). For example, a 32ppm master clock
results in a Lock Range of 198ppm.
PT0100(12/05)
J
E1o
J
T1o
= J
= J
T1o
T1i
x (
x 10
1UIT1
1UIE1
(
-A
2 0
) = J
)
= 20 x 10
T1o
x (
(
644ns
488ns
-18
2 0
= 2.5UI
)
) = 3.3UI
17
Capture Range: The PT7A4402B/4402L DPLL is not at present in
a state of synchronization (lock) with the incoming reference sig-
nal, it is able to initiate (acquire) lock only if the signal`s frequency
is within a certain range, called the Capture Range. For any PLL, no
portion of the Capture Range can fall outside the Lock Range, and,
in general, the Capture Range is more narrow than the Lock Range.
However, owing to the design of its Phase Detector, the PT7A4402B/
4402L`s Capture Range is equal to its Lock Range.
Phase Slope: Phase slope is measured in seconds per second
and is the rate at which a given signal changes phase with
respect to an ideal signal of constant frequency. The given
signal is typically the output signal. The ideal signal is of con-
stant frequency and is nominally equal to the value of the final
output signal or final input signal.
Time Interval Error (TIE): TIE is the time delay between a
given timing signal and an ideal timing signal.
Maximum Time Interval Error (MTIE): MTIE is the maximum
peak to peak delay between a given timing signal and an ideal
timing signal within a particular observation period.
Phase Continuity: Phase continuity is the phase difference
between a given timing signal and an ideal timing signal at the
end of a particular observation period. Usually, the given tim-
ing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the synchronizer after
a signal disturbance due to a reference source switch or a state
change. The observation period is usually the time from the
disturbance, to just after the synchronizer has settled to a steady
state.
For the PT7A4402B/4402L, the output signal phase continuity
is maintained to within 5ns at the instance (over one frame) of
all reference source switches and all state changes. The total
phase shift, depending on the switch or type of state change,
may accumulate up to 200ns over many frames. The rate of
change of the 200ns phase shift is limited to a maximum phase
slope of approximately 5ns/125µs. This meets the AT&T TR62411
maximum phase slope requirement of 7.6ns/125µs (81ns/
1.326ms).
MTIE(S) = TIEmax(t) - TIEmin(t)
T1/E1 System Synchronizer
PT7A4402B/4402L
Data Sheet
Ver:1