pt7a6632 ETC-unknow, pt7a6632 Datasheet
pt7a6632
Available stocks
Related parts for pt7a6632
pt7a6632 Summary of contents
Page 1
... Primary rate interfaces • Basic-rate D-channel controller • Multi-channel HDLC interfaces Introduction The PT7A6632 HDLC controller operates at layer 2 (data link protocol level) of the Open Systems Inter- connection (OSI) reference model. It supports HDLC and ISDN implementations. The PT7A6632 processes data transmitting and re- ceiving communication link ...
Page 2
... Tri-State Serial Data Output TSER ........................................................................................ 14 Channel Operation Modes...................................................................................................... 14 Data Transmission Order ........................................................................................................ 14 Receive Bit-Level Processor ............................................................................................................ 15 Timing .................................................................................................................................... 15 Data Rate Adaptation ............................................................................................................. 15 HDLC Frame Validity ............................................................................................................ 15 Hyperchannel ......................................................................................................................... 15 Channel Operation Modes...................................................................................................... 15 Data Reception Order............................................................................................................. 18 Memory Manager ............................................................................................................................ 18 State / Control Machine ................................................................................................................... 19 PT019(05/02) PT7A6632 32-Channel HDLC Controller Contents 2 Data Sheet Ver:2 ...
Page 3
... Detailed Specifications .............................................................................................................................. 48 Absolute Maximum Ratings ............................................................................................................ 48 Recommended Operating Conditions .............................................................................................. 48 DC Electrical, Power Supply and Capacitance Characteristics ........................................................ 49 AC Characteristics ........................................................................................................................... 50 Serial Interface........................................................................................................................ 50 External Memory Interface ..................................................................................................... 54 Channel Activation/Deactivation ............................................................................................ 56 Input Characteristics ............................................................................................................... 57 Output Characteristics ............................................................................................................ 58 Mechanical Specifications ............................................................................................................... 59 Ordering Information ................................................................................................................................ 60 Notes ......................................................................................................................................................... 61 PT019(05/02) PT7A6632 32-Channel HDLC Controller 3 Data Sheet Ver:2 ...
Page 4
... Block Diagram Figure 2. Block Diagram of PT7A6632 16 A0-A15 8 D0-D7 READ WRITE AS DMND ATTN ATACK SYSACC INTR RESET Pin Information Pin Assignment Table 1. Pin Assignment ...
Page 5
... CH3 13 CH4 14 Rx/Tx 15 TCLK 16 SYSCLK 17 TSER GND 20 GND PT019(05/02) PT7A6632 32-Channel HDLC Controller 60 NC INTR ATTN 57 56 SYSACC GND 55 GND 54 53 GND 68-Pin V 52 PLCC 51 WRITE 50 READ 49 ATACK DMND 48 47 MDFS UAEN ...
Page 6
... PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 7
... PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 8
... PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 9
... CPU. PT7A6632 reads the commands from the external memory and process data channel by channel, totally 64 chan- nels (32 for transmission and 32 for receive). Each channel mode can be set up in external memory independently by CPU. PT7A6632 consists of 4 functional blocks as shown in Figure 2. There are: • Transmit Bit-Level Processor, • ...
Page 10
... Transmit Interface. See Figure 7-10. Data Rate Adaptation The PT7A6632 can adapt the data rate of sub-64kb 8kb the standard 64kb/s bearer rate. A FILL/MASK byte in the transmit command buffer is applied to the data bit by bit to perform data rate adaptation ...
Page 11
... The F-bit time is processed as if the FILL/MASK = 0. However, this actual FILL/MASK does not apply to the F-bit. Figure 8. Transmit Frame Synchronization Timing - CEPT PCM-30 Mode, SIS = 1 Time-slot 31 Bit 7 TCLK TMAX FILL/MASK TSEREN (Low) TSER Data TSEREN (High) Data TSER PT019(05/02) PT7A6632 32-Channel HDLC Controller Channel 1 Bit 8 Bit F Bit 1 Bit 2 Bit 3 High Z Data Data Data 1 1 Data ...
Page 12
... Figure 10. Transmit Frame Synchronization Timing - CEPT PCM-30 Mode, SIS = 0 Time-slot 31 Bit 7 Bit 8 TCLK TMAX FILL/MASK TSEREN (Low) TSER Data TSEREN (High) Data TSER PT019(05/02) PT7A6632 32-Channel HDLC Controller Channel 1 Bit F Bit 1 Bit 2 Bit 3 Bit 4 High Z Data Data Data 1 1 Time Fill ...
Page 13
... Grouping of 64kb/s channels into standard hyperchannels is fixed as shown. Time-slot assignments can be changed (when HCS1 HCS0 = 00) to create flexible hyperchannels by programming command buffers. PT019(05/02) PT7A6632 32-Channel HDLC Controller All channels can also be randomly grouped into flexible hyperchannel (with HCS0 HCS1 = 00). A hyperchannel can contains any number of 64kb/s channels. Details is illustrated in “ ...
Page 14
... After the data in a data buffer is exhausted, the PT7A6632 starts to trans- mit the next byte from the next buffer whose address is speci- fied in the current buffer. The transition to the next buffer is transparent to the CPU while the flow of actual data is main- tained ...
Page 15
... PT7A6632 32-Channel HDLC Controller Receive Mornitor The PT7A6632 monitors the Receive Red Alarm (RRED) in- put. Once the PT7A6632 detects RRED high, it will stop data processing in all receive channels and reports by writing the Status byte. The synchronization will be restored by TMAX and RSYNC signals. ...
Page 16
... PT019(05/02) PT7A6632 32-Channel HDLC Controller • Non-HDLC Signaling Mode In non-HDLC signaling mode, PT7A6632 detects the multiframe alignment sequence. If the alignment sequence is valid, the received data will be sent to the external memory; if not, the data will not be sent to external memory until a valid alignment sequence is detected. The loss of the multiframe alignment will be reported to external memory ...
Page 17
... Proving Period 1 ( one full multiframe) RCLK RSER Bit 7 Bit 8 RRED RSYNC Channel 24, last frame of a multiframe PT019(05/02) PT7A6632 32-Channel HDLC Controller Proving Period 2 Proving Period 3 (one full (one full multiframe) multiframe) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Time-slot 0, first frame of the next ...
Page 18
... T1/E1 trunk interface, instead fetched internally from an inter- mediate buffer in the PT7A6632, in which the data was from a loop mode transmit channel. Thus the data from the external memory is feedback to external memory. Each time only one transmit and one receive channel can be specified in Loop Mode to guarantee normal operation ...
Page 19
... The external memory is managed with minimal inter- vention from the CPU. The CPU sends out an ATTN signal to command PT7A6632 to access the Activation Memory that contains channel number and channel starting address. The SYSACC signal is asserted by PT7A6632 during accessing the Activation Memory ...
Page 20
... Figure 20. External Memory Map - Top Level PT019(05/02) PT7A6632 32-Channel HDLC Controller and Channel Buffer Pointers, providing PT7A6632 such in- formation as channel activation/deactivation, channel direc- tion (transmit or receive) and channel starting addresses. CPU allocates the Channel Starting Pointer for each receive and transmit channel ...
Page 21
... The Activation Memory map is shown in the Figure 21. Channel Activation Byte The Channel Activation Byte are illustrated in the following table 5. The PT7A6632 reads this byte so that gets the channel number, the channel state (active or inactive) and the channel direction (transmit or receive). The PT7A6632 asserts SYSACC when it accesses the Activation Memory ...
Page 22
... PT7A6632 32-Channel HDLC Controller b. MDFS = LOW (iAPX 86 Based) (Contents Rx/Tx Channel Number Byte Addresses xx01 Through xx7F Are Not Used by PT7A6632 Transmit Channels Start Addresses Receive Channels Start Address 22 Data Sheet 1 0 Channel Activation Byte ~ ~ ~ ~ Channel Buffer Pointers ...
Page 23
... Formats are different for Data buffer and Command buffer, and differs with MDFS PT019(05/02) PT7A6632 32-Channel HDLC Controller Buffer Next Buffer Start Address Buffer Size Data length Status byte ~ ~ k Bytes of User s Data or 2 Bytes of Channel Mode & Rate Definition Data ...
Page 24
... Data Processing Memory General The Data Processing Memory refers to Data or Command buff- ers which are linked each other. The PT7A6632 accesses the Data Processing Memory for transmit/receive data and opera- tion commands. Each buffer has following configuration (see Figure 22): • ...
Page 25
... PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 26
... Not used msb i+5 Not Used i IVBA Not used CF/P i INV LOOP SIG HDLC (i+7)+1 (i+7)+ Channel Number (i+7)+ Channel Number (i+7)+j a. MDFS = 1 PT019(05/02) PT7A6632 32-Channel HDLC Controller 0 (Address) i Next Buffer Address i+1 lsb i+2 i+3 i+4 i+5 lsb Data Length (j) i+6 CMND i+7 MPTY Status (1) (i+7)+1 Mode (i+7)+2 FILL/MASK (i+7)+ (i+7)+j 26 Data Sheet (Contents) ...
Page 27
... PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 28
... PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 29
... MASK = 1). See an example in Figure 6 in Section “Transmit Bit-Level Processor” and Table 9. For bit-oriented signaling mode, the FILL/MASK should be set as 1111 1111. If not, the PT7A6632 will not override any other FILL/MASK pattern ...
Page 30
... Buffer Address and send a HDLC flag( non-HDLC octet all-ones to fill the gap, then the PT7A6632 turns to a new buffer chain complete a normal buffer process by setting the MPTY and CF/P bits ...
Page 31
... Following the Descriptors are received data. The number of data bytes are indicated by Data Length which is written by the PT7A6632 after it receives the last byte of an HDLC frame or the HDLC ABORT code, upon the loss of multiframe align- ment error from a non-HDLC signaling channel, or when Re- ceiver Bit-Level Processor detects receive synchronization error caused by RSYN, elastic buffer error or RRED ...
Page 32
... PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 33
... Not used msb i+5 i+6 Not Used x IVBA Not used i INV LOOP SIG HDLC (i+7)+1 (i+7)+ Channel Number (i+7)+ Channel Number (i+7)+j a. MDFS = 1 PT019(05/02) PT7A6632 32-Channel HDLC Controller 0 (Address) i Next Buffer Address i+1 lsb i+2 i+3 i+4 i+5 Data Length (j) lsb i+6 CMND MPTY i+7 Status (1) (i+7)+1 Mode (i+7)+2 FILL/MASK (i+7)+ (i+7)+j 33 Data Sheet ...
Page 34
... PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 35
... PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 36
... PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 37
... FILL/MASK Byte (Rate Definition) The PT7A6632 FILL/MASK byte is used as a masking pattern on the HDLC-formatted (including FLAG, header, data, CRC, and ABORT code) or non-HDLC-formatted data in order to adapt subrates that are multiples of 8kb/s to the 64kb/s rate. The 8-bit sequence is applied to data on a bit by bit basis to remove time-fill (FILL/MASK bit = 0) bits. See an example in Figure 13 in Section “ ...
Page 38
... CPU asserts ATTN. PT7A6632 responds to ATTN, reads channel number, Rx/Tx, Active/Inactive in channel activation byte. PT7A6632 find out the corresponding channel start address and read the start address of the first buffer allocated for the channel. PT7A6632 informs task completion by asserting ATACK. PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 39
... See figure 30 for example. 1: ATTN goes high. 2: PT7A6632 reads activation byte (xx00). 3: PT7A6632 reads the first buffer s starting address (command or data), then sets ATACK, & starts processing that buffer. 4: PT7A6632 resets ATACK after ATTN goes low. 5: PT7A6632 continues processing command or data buffers as controlled by the status of each ...
Page 40
... PT7A6632 32-Channel HDLC Controller 1: ATTN goes high. 2: PT7A6632 accesses Activation Memory (xx00). 3: PT7A6632 reads the first buffer s starting address (command or data), then sets ATACK, & starts processing that buffer. 4: PT7A6632 resets ATACK after ATTN goes low. 5: PT7A6632 continues processing command or data buffers as controlled by the status of each ...
Page 41
... RAM devices may be used. The READ output from the PT7A6632 may be used as an Output Enable (OE) input to the RAM devices. Since the PT7A6632 uses its SYSCLK input to generate various strobes for memory access, the access time requirements are automatically scaled depending on the T1/ CEPT PCM-30 application ...
Page 42
... Memory Address Memory Address Extension The output of CH0 - CH4 and Rx/Tx of the PT7A6632 can be used as upper address bits to extend the 16-bit addresses to 22- bit addresses. See an example in Figure 32. Or these six bits can be mapped by an external lookup table to another set of n bits (where n is specified by the CPU). Since the channel num- ber and Rx/Tx are output by the PT7A6632 well in advance of the 16-bit address, address translation time is not a concern ...
Page 43
... Activation Memory for the address in response to the ATTN assertion. If the 16-bit address is found invalid, the channel will be deactivated. The channel start address is thought in- valid by the PT7A6632 when it is all zero or in form of FFFx. Data/Command Buffer Address -- The PT7A6632 checks next buffer address in each buffer. If found a next buffer address is invalid, the PT7A6632 will set the channel inactive and set the IVBA bit of the current buffer ...
Page 44
... Figure 35. PT7A6632 External Memory Example Interface Waveforms - Single Write Memory Access SYSCLK DMND AS A0-A15 WRITE INTR* D0-D7 Rx/Tx CH0-CH4 * Activated by status write only. Figure 36. PT7A6632 External Memory Example Interface Waveforms - Double Write Memory Access SYSCLK DMND AS A0-A15 WRITE INTR* D0-D7 Rx/Tx CH0-CH4 * Activated by status write only. ...
Page 45
... Figure 37. PT7A6632 External Memory Example Interface Waveforms - Single Read Memory Access SYSCLK DMND AS A0-A15 READ D0-D7 Rx/Tx CH0-CH4 Figure 38. PT7A6632 External Memory Example Interface Waveforms - Read Write Double Memory Access SYSCLK DMND AS A0-A15 READ WRITE D0-D7 INTR* Rx/Tx CH0-CH4 * Activated by status write only. PT019(05/02) ...
Page 46
... Figure 39. PT7A6632 External Memory Example Interface Waveforms - Write Read Double Memory Access SYSCLK DMND AS A0-A15 READ WRITE D0-D7 INTR* Rx/Tx CH0-CH4 Figure 40. PT7A6632 External Memory Example Interface Waveforms - Single Activation Read Memory Access SYSCLK DMND AS A0-A15 READ D0-D7 Rx/Tx CH0-CH4 SYSACC PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 47
... Figure 41. PT7A6632 External Memory Example Interface Waveforms - Single Write Memory Access Plus a Single Activation Read Access SYSCLK DMND AS A0-A15 WRITE INTR* D0-D7 Rx/Tx CH0-CH4 READ SYSACC * Activated by status write only. Figure 42. PT7A6632 External Memory Example Interface Waveforms - Single Write Memory Access Plus a Double ...
Page 48
... Figure 43. PT7A6632 External Memory Example Interface Waveforms - Write/Read Double Memory Access Plus a Single Activation Read Access SYSCLK DMND AS A0-A15 READ WRITE D0-D7 INTR* Rx/Tx CH0-CH4 SYSACC * Activated by status write only. Detailed Specifications Absolute Maximum Ratings Storage Temperature ...................................................... -65 Ambient Temperature with Power Applied ...................... -40 Supply Voltage to Ground Potential (Inputs & ...
Page 49
... Note: o Typical figures are and are for design aid only; not production tested and I are obsolute values PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 50
... TSER (From PT7A6632) TCLK TMAX (From T1/E1 Controller) TSER (From PT7A6632) TCLK TMAX (From T1/E1 Controller) TSER (From PT7A6632) c. Transmit Serial Output - CEPT PCM-30 Mode, TSEREN PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 51
... Figure 45. Clock Timing t R SYSCLK t TCD TCLK PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 52
... Figure 46. TCLK - RCLK Timing t R TCLK t R RCLK PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 53
... PT7A6632 Receive Frame Synchronization Timing Table 29. Receive Frame Synchronization Timing ...
Page 54
... Figure 48. Read Cycle Timing SYSCLK t ASD ADDRESS READ D0-D7 PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 55
... Figure 49. Write Cycle Timing SYSCLK t ASD ADDRESS WRITE t ID INTR t WDD D0-D7 PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 56
... Figure 50. Channel Activation/DeactivationTiming SYSCLK ATTN ATACK PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 57
... PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 58
... PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 59
... Mechanical Specifications Figure 51. 68-Pin PLCC PT019(05/02) PT7A6632 32-Channel HDLC Controller 59 Data Sheet Ver:2 ...
Page 60
... PT019(05/02) PT7A6632 32-Channel HDLC Controller ...
Page 61
... Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT019(05/02) PT7A6632 32-Channel HDLC Controller Notes Pericom Technology Inc. Web-Site: www.pti.com.cn, www.pti-ic.com ...