sp691a Exar Corporation, sp691a Datasheet - Page 13

• Manufacturer Part Number: sp691a
• Description: Low Power Microprocessor Supervisory With Battery Switch-over
• Manufacturer: Exar Corporation

RESET and RESET are asserted for the reset
timeout period (200ms nominal). WDO goes
to logic low and remains low until the next
transition at WDI. Refer to Figure 20. If WDI
is held high or low indefinitely, RESET and
RESET will generate 200ms pulses every 1.6s.
WDO has a 2 x TTL output characteristic.
Selecting an Alternative Watchdog
Timeout Period
The OSC
watchdog are reset timeout periods. Floating
OSC
selects the nominal 1.6s watchdog timeout
period and 200ms reset timout period.
Connecting OSC
connecting OSC
mal watchdog timeout period and a 1.6s timeout
period immediately after reset. The reset timeout
period remains 200ms. Refer to Figure 20.
Select alternative timeout periods by connecting
OSC
between OSC
driving OSC
be found in Figure 21 and Table 1.
Chip-Enable Signal Gating
The SP691A/693A/800L/800M devices
provide internal gating of chip-enable (CE)
signals, to prevent erroneous data from
corrupting the CMOS RAM in the event of a
power failure. During normal operation, the CE
gate is enabled and passes all CE transitions.
When reset is asserted, this path becomes
disabled, preventing erroneous data from
corrupting the CMOS RAM. The SP691A/
693A/800L/800M devices use a series transmission
gate from CE
Date: 4/18/05
Table 1. Reset Pulse Width and Watchdog Timeout Selections
F
F
O
L
L
o l
o l
S
O
O
t a
t a
C
SEL
SEL
W
W
n i
n i
S
E
g
g
L
and OSC
to ground and connecting a capacitor
SEL
E
E
x
IN
x
IN
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
e t
and OSC
e t
IN
. A synopsis of this control can
n r
to CE
n r
SEL
F
and ground, or by externally
l a
IN
O
IN
l a
o l
L
S
O
C
to V
t a
or tying them both to V
C
to ground and floating or
C
o l
W
n i
a
OUT
N I
k c
p
g
OUT
a
IN
. Refer to Figure 16.
n I
t i c
p
r o
selects a 100ms nor-
inputs control the
t u
6 (
0
0
1
4 /
0
N
1
2
7
0
1
r o
4
p
0
6 .
F
c
m
W
m
o l
s
x
l a
a
c
s
C
c t
s k
OUT
)
h
m
d
s
o
13
g
i T
I
m
m
The 10ns maximum CE propagation from CE
to CE
800M devices to be used with most µPs.
Chip-Enable Input
CE
while RESET and/or RESET are asserted.
During a power-down sequence where V
below the reset threshold, CE
impedance state when the voltage at CE
high or 12µs after RESET is asserted,
whichever occurs first. Refer to Figure 19.
During a power-up sequence, CE
impedance until RESET is deasserted.
In the high-impedance mode, the leakage
currents into CE
In the low-impedance mode, the impedance of
CE
the load at CE
The propagation delay through the CE
transmission gate depends on both the source
impedance of the drive to CE
capacitive loading on CE
Chip-Enable Propagation Delay vs. CE
Load Capacitance graph in the Typical
Performance Characteristics section). The
CE propagation delay is defined from the 50%
point on CE
a 50Ω driver and 50pF of load capacitance as in
Figure 22. For minimum propagation delay,
minimize the capacitive load at CE
a low output-impedance driver.
m
2 (
e
e
o
4 .
IN
d
IN
t u
4
a i
4 /
0
appears as a 65Ω resistor in series with
is in high impedance (disabled mode)
P
e t
7
9
OUT
1
1
r e
6
y l
f p
6 .
6 .
c
o i
A
o l
x
s
s
enables the SP691A/693A/800L/
d
t f
c
C
IN
s k
r e
)
OUT
to the 50% point on CE
s
R
e
c
IN
e
.
s
are <1µA over temperature.
t e
R
e
1 (
s
2
t e
0
2
0
IN
i T
0
4 /
2
2
4
assumes a high
m
OUT
IN
7
0
0
8
0
0
p
e
c
remains high
F
o
m
m
o l
IN
OUT
t u
x
c
s
s
(see the
s k
C
OUT
and the
P
and use
)
r e
CC
IN
m
using
o i
s
goes
falls
d
OUT
IN