ICS83026 Integrated Circuit System, ICS83026 Datasheet
ICS83026
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ICS83026 Summary of contents
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... G D ENERAL ESCRIPTION The ICS83026I- low skew, 1-to-2 Dif- ,&6 ferential-to-LVCMOS HiPerClockS™ member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The differential input can accept most differential sig- nal types (LVPECL, LVDS, LVHSTL, HCSL and SSTL) and translate to two single-ended LVCMOS outputs ...
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... www.icst.com/products/hiperclocks.html 2 ICS83026I- KEW - -LVCMOS F TO ANOUT ...
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... www.icst.com/products/hiperclocks.html 3 ICS83026I- KEW - -LVCMOS ANOUT 3.465V -40°C 85° ...
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... www.icst.com/products/hiperclocks.html 4 ICS83026I- KEW - -LVCMOS F TO ANOUT = 1.71V 1.89V -40°C 85° ...
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... www.icst.com/products/hiperclocks.html 5 ICS83026I- KEW - -LVCMOS ANOUT 85° ...
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... PP Qx CLK GND D I IFFERENTIAL NPUT PART 1 V DDO Qx 2 PART 2 V DDO ART TO ART KEW www.icst.com/products/hiperclocks.html 6 ICS83026I- KEW TO -LVCMOS ANOUT UFFER SCOPE OAD EST IRCUIT V Cross Points CMR L EVEL tsk(pp) REV. B NOVEMBER 21, 2002 -2 ...
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... PW odc = t PERIOD t & ERIOD 83026BMI-01 PRELIMINARY D IFFERENTIAL 20% Clock Outputs UTPUT ISE ALL V DDO 2 Q0, Q1 odc & ERIOD www.icst.com/products/hiperclocks.html 7 ICS83026I- KEW TO - -LVCMOS ANOUT UFFER 80% 80% 20 IME V DDO 2 Pulse Width t PERIOD t PW odc = ...
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... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS83026I-0I is: 260 83026BMI-01 PRELIMINARY D IFFERENTIAL R I ELIABILITY ...
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... ° 0 www.icst.com/products/hiperclocks.html 9 ICS83026I- KEW - -LVCMOS ANOUT UFFER ° 8 REV. B NOVEMBER 21, 2002 -2 ...
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... www.icst.com/products/hiperclocks.html 10 ICS83026I- KEW - -LVCMOS ANOUT ° ...