71m6403 Teridian Semiconductor Corporation, 71m6403 Datasheet - Page 14

• Manufacturer Part Number: 71m6403
• Description: Electronic Trip Unit
• Manufacturer: Teridian Semiconductor Corporation

80515 Overview
The 71M6403 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a
5MHz clock results in a processing throughput of 5 MIPS. The 80515 architecture eliminates redundant bus states and im-
plements parallel execution of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore,
most of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (in average) improvement (in
terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Actual processor clocking speed can be adjusted to the total processing demand of the application (current and trip calculations,
memory management, LCD driver management and I/O management) using the I/O RAM register MPU_DIV[2:0].
Typical measurement and circuit breaker functions based on the internal 32-bit compute engine (CE) results are available for the
MPU as part of TERIDIAN’s standard library. A standard ANSI “C” 80515-application programming interface library is available
to help reduce design cycle time.
Memory Organization
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program
memory (Flash), external data memory (physically consisting of XRAM, CE Data RAM, CE Program RAM and I/O RAM), and
internal data memory (Internal RAM). Figure 5 shows the memory map (see also Table 54).
Internal and External Data Memory: Both internal and external data memory are physically located in the 71M6403 IC. Ex-
ternal data memory is only meant to imply external to the 80515 MPU core.
Program Memory: The 80515 can address up to 64KB of program memory space from 0x0000 to 0xFFFF. Program memory is
read when the MPU fetches instructions or performs a MOVC operation.
After reset, the MPU starts program execution from location 0x0000. The lower part of the program memory includes reset and
interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0x0003.
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0xFFFF
0x0000
Program memory
Flash memory
©
2006 TERIDIAN Semiconductor Corporation
Figure 5: Memory Map
0xFFFF
0x4000
0x3FFF
0x3000
0x2FFF
0x2100
0x20FF
0x2000
0x1FFF
0x1400
0x13FF
0x1000
0x0FFF
0x0800
0x07FF
0x0000
80515 MPU Core
External data memory
---
CE PRAM
---
I/O RAM
---
CE DRAM
---
XRAM
Electronic Trip Unit
0xFF
0x00
Internal data memory
SFRs, RAM,
reg. banks
71M6403
SEPTEMBER 2006
REV 1.0