xr20v2172 Exar Corporation, xr20v2172 Datasheet - Page 52

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xr20v2172

Manufacturer Part Number
xr20v2172
Description
Two Channel I2c/spi Uart With 64-byte Fifo And Rs232 Transceiver
Manufacturer
Exar Corporation
Datasheet
REV. 1.0.0
GENERAL DESCRIPTION................................................................................................ 1
PIN DESCRIPTIONS ....................................................................................................... 3
1.0 PRODUCT DESCRIPTION ...................................................................................................................... 6
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 7
3.0 UART INTERNAL REGISTERS............................................................................................................. 21
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 23
A
F
ORDERING INFORMATION
EATURES
PPLICATIONS
2.1 CPU INTERFACE ................................................................................................................................................ 7
2.2 I2C-BUS ADDRESSING ...................................................................................................................................... 8
2.3 DEVICE RESET ................................................................................................................................................... 9
2.4 INTERNAL REGISTERS...................................................................................................................................... 9
2.5 IRQ# OUTPUT ..................................................................................................................................................... 9
2.6 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 10
2.7 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 10
2.8 TRANSMITTER.................................................................................................................................................. 12
2.9 RECEIVER ......................................................................................................................................................... 14
2.10 AUTO RTS (HARDWARE) FLOW CONTROL ................................................................................................ 15
2.11 AUTO RTS HALT AND RESUME .................................................................................................................. 15
2.12 AUTO CTS FLOW CONTROL........................................................................................................................ 15
2.13 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 17
2.14 SPECIAL CHARACTER DETECT.................................................................................................................. 17
2.15 SLEEP MODE WITH AUTO WAKE-UP ......................................................................................................... 17
2.16 INFRARED MODE (UART CHANNEL B ONLY)............................................................................................. 19
2.17 INTERNAL LOOPBACK................................................................................................................................. 20
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 23
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 23
F
F
F
F
F
T
T
T
T
T
F
F
T
F
F
F
F
F
F
F
T
T
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
2.1.1 I2C-BUS INTERFACE ..................................................................................................................................................... 7
2.2.1 SPI BUS INTERFACE ..................................................................................................................................................... 9
2.8.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 12
2.8.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... 13
2.8.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 13
2.9.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .............................................................................................. 14
2.15.1 PARTIAL SLEEP MODE............................................................................................................................................. 17
2.15.2 FULL SLEEP MODE ................................................................................................................................................... 18
1: XR20V2172 I2C A
2: I2C S
3: SPI F
4: IRQ# P
5: IRQ# P
6: T
7: UART INTERNAL REGISTER ADDRESSES .............................................................................................................. 21
8: INTERNAL REGISTERS DESCRIPTION. S
1. XR20V2172 B
2. P
3. I2C S
4. M
5. M
6. T
7. B
8. T
9. T
10. R
11. R
12. A
13. I
14. I
2.15.1.1 UART
2.15.1.2 UART
.................................................................................................................................................... 1
YPICAL DATA RATES WITH A
YPICAL OSCILLATOR CONNECTIONS
RANSMITTER
RANSMITTER
IN
AUD
ASTER
ASTER
NFRARED
NTERNAL
UTO
ECEIVER
ECEIVER
.............................................................................................................................................. 1
O
UB
IRST
UT
R
TART AND
IN
IN
-A
RTS
ATE
W
R
A
O
O
B
DDRESS
EADS
SSIGNMENT
PERATION FOR
PERATION
RITES
YTE
L
T
O
O
G
OOP
AND
RANSMIT
PERATION IN NON
PERATION IN
ENERATOR
IN SLEEP MODE
ACTIVE
O
O
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
LOCK
............................................................................................................................... 2
F
PERATION IN NON
PERATION IN
F
S
ORMAT
T
CTS F
B
ROM
DDRESS
TOP
............................................................................................................................................................ 8
O
ACK
D
S
,
F
..................................................................................................................................................... 2
IAGRAM
CHARGE PUMP OF
D
LAVE
OR
C
S
................................................................................................................................................. 20
ATA
LAVE
LOW
ONDITIONS
.................................................................................................................................................. 9
............................................................................................................................................... 11
T
R
M
FIFO
RANSMITTER
24 MH
ECEIVER
(V2172) ............................................................................................................................... 7
E
AP
FIFO
C
, RS-232
NCODING AND
......................................................................................................................................... 1
(V2172) ............................................................................................................................ 7
-FIFO M
ONTROL
TABLE OF CONTENTS
....................................................................................................................................... 8
AND
-FIFO M
Z CRYSTAL OR EXTERNAL CLOCK AT
AND
................................................................................................................................. 7
............................................................................................................................... 10
............................................................................................................................. 10
A
UTO
TRANSCEIVER ACTIVE
ODE
O
F
.......................................................................................................................... 9
RS-232
LOW
PERATION
ODE
RTS F
.................................................................................................................. 14
R
HADED BITS ARE ENABLED WHEN
ECEIVE
C
.............................................................................................................. 13
ONTROL
TRANSCEIVER SHUT DOWN
LOW
....................................................................................................... 16
1
D
ATA
C
M
ONTROL
ODE
D
......................................................................................... 17
ECODING
..................................................................................... 13
M
ODE
16X S
.......................................................................... 19
....................................................................... 15
.................................................................. 18
AMPLING
EFR B
IT
................................................... 12
-4=1 ......................................... 22
XR20V2172

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