xr20v2170 Exar Corporation, xr20v2170 Datasheet - Page 11

• Manufacturer Part Number: xr20v2170
• Description: I2c/spi Uart With 64-byte Fifo And Rs232 Transceiver
• Manufacturer: Exar Corporation

REV. 1.0.0
value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed
during initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor
and the DLD register provides the fractional part of the dvisior. The four lower bits of the DLD are used to select
a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator
Registers DLL, DLM and DLD provides the capability for selecting the operating data rate.
standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used
(MCR bit-7 = 1), the output data rate will be 4 times less than that shown in
data rates would double and at 4X sampling rate, these data rates would quadruple. Also, when using 8X
sampling mode, the bit time will have a jitter of
When using 4X sampling mode, the bit time will have a jitter of ± 1/8 whenever DLD is non-zero, odd and not a
multiple of 4. When using a non-standard data rate crystal or external clock, the divisor value can be
calculated with the following equation(s):
The closest divisor that is obtainable in the V2170 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
F
IGURE
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’
8. B
AUD
XTAL2
XTAL1
R
ATE
G
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
ENERATOR
Crystal
Buffer
Osc/
DLL = TRUNC(Required Divisor) & 0xFF
DLM = TRUNC(Required Divisor) >> 8
I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
Divide by 4
Divide by 1
Prescaler
Prescaler
±
1/16 whenever the DLD is non-zero and is an odd number.
11
MCR Bit-7=0
MCR Bit-7=1
(default)
DLL, DLM and DLD
Fractional Baud
Rate Generator
Registers
Logic
Table
16X or 8X or 4X
6. At 8X sampling rate, these
and Receiver
to Transmitter
Rate Clock
Sampling
Table 6
XR20V2170
shows the