xr20m1170 Exar Corporation, xr20m1170 Datasheet - Page 38
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xr20m1170
Manufacturer Part Number
xr20m1170
Description
I2c/spi Uart With 64-byte Fifo
Manufacturer
Exar Corporation
Datasheet
1.XR20M1170.pdf
(60 pages)
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XR20M1170
I2C/SPI UART WITH 64-BYTE FIFO
EFCR[6]: Reserved
EFCR[5]: Auto RS-485 Polarity Inversion
This bit changes the polarity of the Auto RS-485 Half-Duplex Direction Control output (RTS#). This bit will only
affect the behavior of the RTS# output if EFCR[4] = 1. See
on page 19
•
•
EFCR[4]: Auto RS-485 Enable
This bit enables the RTS# output as the Auto RS-485 Half-Duplex Direction Control output. See
2.14, Auto RS485 Half-duplex Control” on page 19
•
•
EFCR[3]: Reserved
EFCR[2]: Transmitter Disable
UART does not send serial data out on the TX output pin, but the TX FIFO will continue to receive data from
CPU until full. Any data in the TSR will be sent out before the trasnmitter goes into disable state.
•
•
EFCR[1] = Receiver Disable
UART will stop receiving data immediately once this bit is set to a Logic 1. Any data that is being received in
the TSR will be received correctly and sent to the RX FIFO.
•
•
EFCR[0]: 9-bit or Multidrop Mode Enable
This bit enables 9-bit or Multidrop mode. See
for complete details.
•
•
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed.
FRACTIONAL DIVISOR” ON PAGE 12.
DLD[5:4]: Sampling Rate Select
4.20
Logic 0 = RTS# output is LOW when transmitting and HIGH when receiving.
Logic 1 = RTS# output is HIGH when transmitting and LOW when receiving.
Logic 0 = RTS# output can be used for Auto RTS Hardware Flow Control or as a general purpose output.
Logic 1 = RTS# output enabled as the Auto RS-485 Half-Duplex Direction Control output.
Logic 0 = Transmitter is enabled
Logic 1 = Transmitter is disabled
Logic 0 = Receiver is enabled
Logic 1 = Receiver is disabled
Logic 0 = Normal 8-bit mode
Logic 1 = Enable 9-bit or Multidrop mode
Baud Rate Generator Registers (DLL, DLM and DLD[3:0]) - Read/Write
for complete details.
“Section 2.14, Auto RS485 Half-duplex Control” on page 19
SEE”PROGRAMMABLE BAUD RATE GENERATOR WITH
38
for complete details.
“Section 2.14, Auto RS485 Half-duplex Control”
REV. 1.0.0
“Section