xr21b1411 Exar Corporation, xr21b1411 Datasheet - Page 6

• Manufacturer Part Number: xr21b1411
• Description: Enhanced 1-ch Full-speed Usb Uart
• Manufacturer: Exar Corporation

XR21B1411
ENHANCED 1-CH FULL-SPEED USB UART
the start bit followed by the data bits (starting with the LSB), inserts the proper parity-bit if enabled, and adds
the stop-bit(s). The transmitter can be configured for 7 or 8 data bits with or without parity or 9 data bits without
parity.
If 7 or 8 bit data with parity is selected, the TX FIFO contains 8 bits data and the parity bit is automatically
generated and transmitted. If 9 bit data is selected, parity cannot be generated. The 9th bit will always be a ’0’
unless the wide mode is enabled.
When 9 bit data and the wide mode are both selected, 2 bytes from the USB host are used to form 9 bit data
which is serialized and transmitted on the UART TX pin. The first byte received into the TX FIFO forms the first
8 bits of data and the least significant bit of the second byte forms the 9th bit data. The remaining 7 bits of the
second byte are discarded. The wide mode can be enabled via the WIDE_MODE register at address 0xD02.
The receiver consists of a 384-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in the
RSR via the RX pin is transferred into the RX FIFO along with any error tags such as Framing, Parity, Break
and Overrun errors. Data from the RX FIFO can be sent to the USB host by sending a bulk-in packet.
If the wide mode is not enabled, then 7 or 8 bits of data are transferred without any error tags (including parity)
to the USB host. In 9-bit data mode, the B1411 will forward only 8 bit data to the USB host and the 9th bit of
the character will be dropped.
In wide mode, the B1411 receives a 7, 8 or 9 bit character and then forwards the character along with 3
associated error bits to the USB host in two bytes. If data is 7 or 8 bits, a parity bit is also received and
checked. If data is 9 bits, no parity is checked. The 9th bit of data is in bit position 0 along with the 3 error bits,
break, frame error and overrun error flags in bit positions 1, 2 & 3 respectively. In wide mode, the error flags
are tied to the character that they accompany. The wide mode can be enabled via the WIDE_MODE register
at address 0xD02.
Error flags are also available from the ERROR_STATUS register and the interrupt packet, however these flags
are historical flags indicating that an error has occurred since the previous request. Therefore, no conclusion
can be drawn as to which specific byte(s) may have contained an actual error in this manner.
1.3.1.1
1.3.2
1.3.2.1
Receiver
Wide mode Transmit
Wide mode Receive
2nd byte
2nd byte
1st byte
1st byte
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
x x x x O F B P
x x x x O F B 8
7 or 8 bit m ode
9 bit m ode
F
IGURE
3. R
ECEIVE
6
D
B = B reak
F = Fram ing E rror
O = O verrun E rror
B = B reak
F = Fram ing E rror
P = P arity E rror (= ‘0’ if not enabled)
x = ‘0’
O = O verrun E rror
ATA
x = ‘0’
7 = ‘0’ in 7 bit m ode
F
ORMAT
REV. 1.1.0