xr21b1411 Exar Corporation, xr21b1411 Datasheet - Page 14

• Manufacturer Part Number: xr21b1411
• Description: Enhanced 1-ch Full-speed Usb Uart
• Manufacturer: Exar Corporation

XR21B1411
ENHANCED 1-CH FULL-SPEED USB UART
The contents of this register, if programmed, are used to overwrite the GPIO_MODE register at address 0xC0C
when a CDC command is sent from a standard CDC-ACM driver to the B1411 device. Note that this register
can only be programmed from the OTP. Since a standard CDC_ACM driver is unaware of UART registers in
the B1411, this register may be utilized to program UART settings from power-up. When a custom driver is
used, the custom driver should program these settings directly into the GPIO_MODE register.
Bit fields in this register are the same as those in the GPIO_MODE register. Refer to
GPIO_MODE Register Description (Read / Write)” on page
The contents of this register, if programmed, are used to overwrite the GPIO_DIRECTION register at address
0xC0D when a CDC command is sent from a standard CDC-ACM driver to the B1411 device. Note that this
register can only be programmed from the OTP. Since a standard CDC_ACM driver is unaware of UART
registers in the B1411, this register may be utilized to program UART settings from power-up. When a custom
driver is used, the custom driver should program these settings directly into the GPIO_DIRECTION register.
Bit fields in this register are the same as those in the GPIO_DIRECTION register. Refer to
GPIO_DIRECTION Register Description (Read / Write)” on page
The contents of this register, if programmed, are used to overwrite the GPIO_INT_MASK register at address
0xC11 when a CDC command is sent from a standard CDC-ACM driver to the B1411 device. Note that this
register can only be programmed from the OTP. Since a standard CDC_ACM driver is unaware of UART
registers in the B1411, this register may be utilized to program UART settings from power-up. When a custom
driver is used, the custom driver should program these settings directly into the GPIO_INT_MASK register.
Bit fields in this register are the same as those in the GPIO_INT_MASK register. Refer to
GPIO_INT_MASK Register Description (Read / Write)” on page
Ensure that both UART Tx and UART Rx are disabled before writing to any other UART registers except for the
GPIO_SET, GPIO_CLEAR and Tx Break registers.
UART_ENABLE[0]: Enable UART TX
UART_ENABLE[1]: Enable UART RX
UART_ENABLE[11:2]: Reserved
These bits are reserved and should remain ’0’.
3.1.1.3
3.1.1.4
3.1.1.5
3.1.1.6
Logic 0 = UART TX disabled.
Logic 1 = UART TX enabled.
Logic 0 = UART RX disabled.
Logic 1 = UART RX enabled.
CDC_ACM_GPIO_MODE Register Description (Read / Write)
CDC_ACM_GPIO_DIRECTION Register Description (Read / Write)
CDC_ACM_GPIO_INT_MASK Register Description (Read / Write)
UART_ENABLE Register Description (Read / Write)
14
17.
18.
17.
“Section 3.1.1.13,
“Section 3.1.1.18,
“Section 3.1.1.14,
REV. 1.1.0