sc16is760ipw NXP Semiconductors, sc16is760ipw Datasheet - Page 21

• Manufacturer Part Number: sc16is760ipw
• Description: Single Uart With I2c-bus/spi Interface, 64 Bytes Of Transmit And Receive Fifos, Irda Sir Built-in Support
• Manufacturer: NXP Semiconductors

Table 10.
Register
address
General register set
0x00
0x00
0x01
0x02
0x02
0x03
0x04
0x05
0x06
0x07
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
SC16IS740/750/760 internal registers
Register
RHR
THR
IER
FCR
IIR
LCR
MCR
LSR
MSR
SPR
TCR
TLR
TXLVL
RXLVL
IODir
IOState
IOIntEna
reserved
IOControl
EFCR
[6]
[7]
[7]
[4]
[4]
[4]
[3]
[1]
[4]
Bit 7
bit 7
bit 7
CTS
interrupt
enable
RX trigger
level (MSB)
FIFO enable FIFO enable
Divisor Latch
Enable
clock
divisor
FIFO data
error
CD/(IO6)
bit 7
bit 7
bit 7
bit 7
bit 7
bit 7
bit 7
bit 7
reserved
reserved
IrDA mode
(slow/ fast)
[2]
[2]
[3]
[3]
[4]
[8]
Bit 6
bit 6
bit 6
RTS interrupt
enable
RX trigger
level (LSB)
set break
IrDA mode
enable
THR and
TSR empty
RI/(IO7)
bit 6
bit 6
bit 6
bit 6
bit 6
bit 6
bit 6
bit 6
reserved
reserved
reserved
[2]
[2]
[4]
[3]
[3]
[3]
Bit 5
bit 5
bit 5
Xoff
TX trigger
level (MSB)
interrupt
priority bit 4
set parity
Xon Any
THR empty
DSR/ (IO4)
bit 5
bit 5
bit 5
bit 5
bit 5
bit 5
bit 5
bit 5
reserved
reserved
auto RS-485
RTS output
inversion
[2]
[2]
[3]
[3]
[4]
[2]
[2]
Bit 4
bit 4
bit 4
Sleep mode
TX trigger
level (LSB)
interrupt
priority bit 3
even parity
loopback
enable
break interrupt framing error
CTS
bit 4
bit 4
bit 4
bit 4
bit 4
bit 4
bit 4
bit 4
reserved
reserved
auto RS-485
RTS direction
control
[3]
[3]
[2]
[2]
[2]
Bit 3
bit 3
bit 3
modem status
interrupt
reserved
interrupt
priority bit 2
parity enable
reserved
bit 3
bit 3
bit 3
bit 3
bit 3
bit 3
bit 3
bit 3
reserved
UART
software reset
reserved
CD/ (IO6)
[3]
[3]
[3]
[3]
[4]
Bit 2
bit 2
bit 2
receive line
status interrupt
TX FIFO
reset
interrupt
priority bit 1
stop bit
TCR and TLR
enable
parity error
bit 2
bit 2
bit 2
bit 2
bit 2
bit 2
bit 2
bit 2
reserved
reserved
transmitter
disable
RI/(IO7)
[5]
[2]
[3]
[3]
[4]
Bit 1
bit 1
bit 1
THR empty
interrupt
RX FIFO
reset
interrupt
priority bit 0
word length
bit 1
RTS
overrun error
bit 1
bit 1
bit 1
bit 1
bit 1
bit 1
bit 1
bit 1
reserved
I/O[7:4] or RI,
CD, DTR, DSR
receiver
disable
DSR/ (IO4)
[5]
[3]
[4]
Bit 0
bit 0
bit 0
RX data
available
interrupt
FIFO enable
interrupt status R
word length
bit 0
DTR/(IO5)
data in receiver R
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
reserved
latch
9-bit mode
enable
CTS
[3]
[4]
R/W
R
W
R/W
W
R/W
R/W
R
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W