sc16c852 NXP Semiconductors, sc16c852 Datasheet - Page 10

• Manufacturer Part Number: sc16c852
• Description: 2.5 V To 3.3 V Dual Uart, 5 Mbit/s Max. With 128-byte Fifos, Infrared Irda And 16 Mode Or 68 Mode Bus Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
6. Functional description
SC16C852_1
Product data sheet
The SC16C852 provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit
to the data character. The parity bit is checked by the receiver for any transmission bit
errors. The electronic circuitry to provide all these functions is fairly complex, especially
when manufactured on a single integrated silicon chip. The SC16C852 represents such
an integration with greatly enhanced features. The SC16C852 is fabricated with an
advanced CMOS process.
The SC16C852 is an upward solution to the SC16C652B that provides a dual UART
capability with 128 bytes of transmit and receive FIFO memory, instead of 32 bytes for the
SC16C652 and 16 bytes in the SC16C2550. The SC16C852 is designed to work with high
speed modems and shared network environments that require fast data processing time.
Increased performance is realized in the SC16C852 by the transmit and receive FIFOs.
This allows the external processor to handle more networking tasks within a given time. In
addition, the four selectable receive and transmit FIFO trigger interrupt levels are provided
in SC16C652 mode, or 128 programmable levels are provided in the extended mode for
maximum data throughput performance especially when operating in a multi-channel
environment (see
greatly reduces the bandwidth requirement of the external controlling CPU and increases
performance. A low power pin (LOWPWR) is provided to further reduce power
consumption by isolating the host bus interface.
The SC16C852 is capable of operation up to 5 Mbit/s with an external 80 MHz clock. With
a crystal, the SC16C852 is capable of operation up to 1.5 Mbit/s.
The rich feature set of the SC16C852 is available through internal registers. These
features are: selectable and programmable receive and transmit FIFO trigger levels,
selectable TX and RX baud rates, and modem interface controls, and are all standard
features. Following a power-on reset, an external reset, or a software reset, the
SC16C852 is software compatible with the previous generation, SC16C2550,
SC16C652B, and ST16C2450.
Section 6.2 “Extended mode (128-byte
Rev. 01 — 31 August 2009
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
FIFO)”). The FIFO memory
SC16C852
© NXP B.V. 2009. All rights reserved.
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