sc16c654 NXP Semiconductors, sc16c654 Datasheet - Page 16

• Manufacturer Part Number: sc16c654
• Description: Quad Uart With 64-byte Fifo And Infrared Irda Encoder/decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 11617
Product data
6.11 Programmable baud rate generator
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C654/654D FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time.
In the 16 mode for the PLCC68 package, the system/board designer can optionally
provide software controlled 3-State interrupt operation. This is accomplished by
INTSEL and MCR[3]. When INTSEL interface pin is left open or made a logic 0,
MCR[3] controls the 3-State interrupt outputs, INTA-INTD. When INTSEL is a logic 1,
MCR[3] has no effect on the INTA-INTD outputs, and the package operates with
interrupt outputs enabled continuously.
The SC16C654/654D supports high speed modem technologies that have increased
input data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate.
A 128.0 kbit/s ISDN modem that supports data compression may need an input
data rate of 460.8 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is
capable of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as
required for supporting a 5 Mbits/s data rate. The SC16C654/654D can be configured
for internal or external clock operation. For internal clock oscillator operation, an
industry standard microprocessor crystal (parallel resonant/22-33 pF load) is
connected externally between the XTAL1 and XTAL2 pins (see
Alternatively, an external clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom rates (see
The generator divides the input 16 clock by any divisor from 1 to 2
SC16C654/654D divides the basic external clock by 16. Further division of this 16
clock provides two table rates to support low and high data rate applications using the
Fig 6. Crystal oscillator connection.
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
Rev. 04 — 19 June 2003
C1
47 pF
1.8432 MHz
X1
C2
100 pF
SC16C654/654D
1.8432 MHz
C1
22 pF
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
X1
1.5 k
Table
C2
47 pF
Figure
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