xr17l154iv Exar Corporation, xr17l154iv Datasheet - Page 16

• Manufacturer Part Number: xr17l154iv
• Description: 3.3v Pci Bus Quad Uart
• Manufacturer: Exar Corporation

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The first four bits of the Sleep register enables each UART channel separately to enter Sleep mode. The upper
bits 4 to 7 are reserved. Sleep mode reduces power consumption when the system needs to put the UART(s)
to idle. The UART enters Sleep mode when there is no interrupt pending. When all 4 UARTs are put to sleep,
the on-chip oscillator shuts off to further conserve power. In this case, the quad UART is awaken by any of the
UART channel on from a receive data byte or a change on the serial port. The UART is ready after 32 crystal
clocks to ensure full functionality. Also, a special interrupt is generated with an indication of no pending
interrupt. Logic 0 (default) is disable and logic 1 is enable to Sleep mode.
There are 2 internal registers that provide device identification and revision, DVID and DREV registers. The 8-
bit content in the DVID register provides device identification. A return value of 0x24 from this register indicates
the device is an XR17L154 or an XR17C154. The DREV register returns an 8-bit value of 0x01 for revision A
with 0x02 equals to revision B and so forth. This information is very useful to the software driver for identifying
which device it is communicating with and to keep up with revision changes.
DVID [15:8] - (default 0x24)
Device identification for the type of UART. The upper nibble indicates it is a XR17Cxxx series with lower nibble
indicating the number of channels.
Examples:
XR17C158 = 0x28
XR17L154 or XR17L154 = 0x24
XR17C152 or XR17L152 = 0x22
DREV [7:0] - (default (0x01)
Revision number of the XR17L154. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth.
REGB [23:16] - (default 0x00)
REGB register provides a control for simultaneous write to all 4 UARTs configuration register or individually.
This is very useful for device initialization in the power up and reset routines. Also, the register provides a
facility to interface to the non-volatile memory device such as a 93C46 EEPROM. In embedded applications,
the user can use this facility to store proprietary data.
DISCONTINUED
1.2.6
1.2.7
REGB[16] (Read/Write)
REGB[19:17]
REGB[20] (Write-Only)
REGB[21] (Write-Only)
REGB[22] (Write-Only)
REGB[23] (Read-Only)
1.2.8
SLEEP [31:24] - (default 0x00)
Device Identification and Revision
RGEB Register
Logic 0 (default) write to each UART configuration registers individually.
Logic 1 enables simultaneous write to all 4 UARTs configuration register.
Reserved
Control the EECK, clock, output (pin 116) on the EEPROM interface.
Control the EECS, chips select, output (pin 115) to the EEPROM device.
EEDI (pin 114) data input. Write data to the EEPROM device.
EEDO (pin 113) data output. Read data from the EEPROM device.
B it-7 Bit-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
R svd
Individual U A R T C hannel S leep E nable
R svd R svd R svd
SLEEP Register
16
C h-3 C h-2 C h-1 C h-0
3.3V PCI BUS QUAD UART
XR17L154
REV. 1.1.0