xr16c2550ip Exar Corporation, xr16c2550ip Datasheet - Page 16
![no-image](/images/manufacturer_photos/0/2/243/exar_corporation_sml.jpg)
xr16c2550ip
Manufacturer Part Number
xr16c2550ip
Description
Dual Uart With 16-byte Transmit And Receive Fifos
Manufacturer
Exar Corporation
Datasheet
1.XR16C2550IP.pdf
(38 pages)
XR16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
.
See “Receiver” on page 12.
See “Transmitter” on page 11.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
A
A2-A0
DDRESS
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
N
MCR
MSR
RHR
THR
FCR
SPR
DLM
LCR
LSR
R
DLL
IER
ISR
AME
EG
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR
RD/WR
R
W
WR
WR
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
Enabled
Trigger
Enable
Global
FIFOs
B
Error
Input
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
T
CD#
IT
ABLE
0
0
-7
7: INTERNAL REGISTERS DESCRIPTION
RX FIFO
Enabled
Trigger
Set TX
THR &
Empty
FIFOs
Break
B
Input
Bit-6
Bit-6
TSR
Bit-6
Bit-6
Bit-6
RI#
IT
0
0
-6
16C550 Compatible Registers
Baud Rate Generator Divisor
Set Par-
Empty
DSR#
B
Input
Bit-5
Bit-5
THR
Bit-5
Bit-5
Bit-5
ity
IT
0
0
0
0
-5
16
Internal
Enable
Parity
Loop-
Break
CTS#
B
Even
Input
back
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
RX
IT
0
0
0
-4
Modem
Enable
Source
Enable
Enable
Enable
Output
OP2#/
Fram-
Parity
Mode
B
Delta
DMA
Error
Bit-3
Bit-3
Stat.
Bit-3
CD#
Bit-3
Bit-3
Bit-3
INT
INT
Int.
RX
ing
IT
-3
RX Line
Enable
Source
(OP1#)
Reset
Rsrvd
Parity
B
Delta
FIFO
Error
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Stat.
Stop
Bits
INT
RI#
Int.
RX
TX
IT
-2
Control
Enable
Source
Length
Output
Empty
DSR#
Reset
RTS#
Word
Over-
B
FIFO
Delta
Error
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
run
RX
RX
TX
Int
IT
-1
Enable
Source
Enable
Control
Length
Output
Ready
FIFOs
DTR#
CTS#
B
Word
Delta
Bit-0
Bit-0
Data
Bit-0
Bit-0
Data
Bit-0
Bit-0
Bit-0
INT
RX
Int.
RX
IT
-0
xr
LCR[7] = 0
LCR[7] = 1
C
OMMENT
REV. 1.0.1