xr16c2852ij Exar Corporation, xr16c2852ij Datasheet - Page 3

• Manufacturer Part Number: xr16c2852ij
• Description: 2.97v To 5.5v Dual Uart With 128-byte Fifos
• Manufacturer: Exar Corporation

xr
REV. 2.1.1
PIN DESCRIPTIONS
Pin Description
DATA BUS INTERFACE
MODEM OR SERIAL I/O INTERFACE
TXRDYA#
TXRDYB#
CHSEL
N
IOW#
IOR#
INTB
INTA
CS#
TXA
D7
D6
D5
D4
D3
D2
D1
D0
A2
A1
A0
AME
44-PLCC
P
15
14
10
24
20
18
16
34
17
32
38
IN
9
8
7
6
5
4
3
2
1
#
T
I/O
YPE
O
O
O
O
O
I
I
I
I
I
UART channel A Transmitter Ready (active low). The output provides the TX
FIFO/THR status for transmit channel A. See
not used, leave it unconnected.
Address data lines [2:0]. These 3 address lines select one of the internal registers in
UART channel A/B during a data bus transaction.
Data bus lines [7:0] (bidirectional).
Input/Output Read Strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to
read it on the rising edge.
Input/Output Write Strobe (active low). The falling edge instigates an internal write
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
UART chip select (active low). This function selects channel A or B in accordance
with the logical state of the CHSEL pin. This allows data to be transferred between the
user CPU and the 2852.
Channel Select - UART channel A or B is selected by the logical state of this pin when
the CS# pin is LOW. A LOW on the CHSEL selects the UART channel B while a HIGH
selects UART channel A. Normally, CHSEL could just be an address line from the
user CPU such as A4. Bit-0 of the Alternate Function Register (AFR) can temporarily
override CHSEL function, allowing the user to write to both channel register simulta-
neously with one write cycle when CS# is LOW. It is especially useful during the ini-
tialization routine.
UART channel A Interrupt output (active high). A logic high indicates channel A is
requesting for service. For more details, see
UART channel B Interrupt output (active high). A logic high indicates channel B is
requesting for service. For more details, see
UART channel B Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel B.
used, leave it unconnected.
UART channel A Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is a logic 0. If this output is not used, leave it
unconnected.
3
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
See
D
ESCRIPTION
Table 2 on page
Figures 20
Figures 20
Table 2 on page
-
-
9.
25
25
If this output is not
.
.
9.
XR16C2852
If this output is