xr16c2852ij Exar Corporation, xr16c2852ij Datasheet - Page 11

• Manufacturer Part Number: xr16c2852ij
• Description: 2.97v To 5.5v Dual Uart With 128-byte Fifos
• Manufacturer: Exar Corporation

xr
REV. 2.1.1
divisor between 1 and (2
clock is used by the transmitter for data bit shifting and receiver for data sampling.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate.
clock at 16X sampling rate clock rate. When using a non-standard data rate crystal or external clock, the
divisor value can be calculated for DLL/DLM with the following equation.
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 128 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
O
2.11
UTPUT
MCR Bit-7=1
230.4k
115.2k
19.2k
38.4k
57.6k
1200
2400
4800
9600
100
600
Data Rate
Transmitter
F
T
IGURE
ABLE
XTAL1
XTAL2
O
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
UTPUT
Table 5
6. B
5: T
MCR Bit-7=0
(D
153.6k
230.4k
460.8k
921.6k
EFAULT
19.2k
38.4k
76.8k
16
2400
4800
9600
YPICAL DATA RATES WITH A
AUD
400
Data Rate
-1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate
shows the standard data rates available with a 14.7456 MHz crystal or external
R
Crystal
Buffer
Osc/
)
ATE
G
Clock (Decimal)
D
ENERATOR AND
IVISOR FOR
2304
384
192
96
48
24
12
6
4
2
1
Divide by 4
Divide by 1
Prescaler
Prescaler
16x
14.7456 MH
P
D
11
RESCALER
IVISOR FOR
Clock (HEX)
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
MCR Bit-7=0
MCR Bit-7=1
(default)
900
180
C0
0C
60
30
18
06
04
02
01
Z CRYSTAL OR EXTERNAL CLOCK
16x
Baud Rate
DLL and DLM
Generator
Registers
Logic
V
ALUE
P
ROGRAM
DLM
09
01
00
00
00
00
00
00
00
00
00
(HEX)
Rate Clock to
Transmitter
Sampling
16X
V
ALUE
P
ROGRAM
DLL
C0
0C
00
80
60
30
18
06
04
02
01
(HEX)
XR16C2852
D
E
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)