xr16c864iq Exar Corporation, xr16c864iq Datasheet - Page 11

• Manufacturer Part Number: xr16c864iq
• Description: Quad Uart With Rx/tx Fifo Counters And 128-byte Fifo
• Manufacturer: Exar Corporation

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REV. 2.0.1
Each UART channel in the 864 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the 864 offers enhanced feature registers (EMSR, FLVL,
EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware flow control,
Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO trigger
level control, and FIFO level counters. All the register functions are discussed in full detail later in
UART INTERNAL REGISTERS” on page
The interrupt outputs change according to the operating mode and enhanced features setup.
summarize the operating behavior for the transmitter and receiver. Also see
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2.6
2.7
INT Pin
INT Pin
INT Pin
Channels A-D Internal Registers
INT Ouputs for Channels A-D
FCTR
Bit-3
0
1
0 = no data
1 = 1 byte
0 = a byte in THR
1 = THR empty
0 = a byte in THR
1 = transmitter empty
(FIFO D
FCR B
(FIFO D
T
FCR B
ABLE
T
ABLE
IT
ISABLED
-0 = 0
IT
ISABLED
CS#
3: INT P
-0 = 0
1
0
0
0
0
4: INT P
)
T
ABLE
N/A
)
A4
0
0
1
1
INS
IN
0 = FIFO below trigger level
1 = FIFO above trigger level
O
2: C
O
N/A
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO
empty
0 = FIFO above trigger level
1 = FIFO below trigger level or
transmitter empty
PERATION FOR
A3
22.
0
1
0
1
PERATION FOR
HANNEL
(DMA Mode Disabled)
(DMA Mode Disabled)
FCR Bit-3 = 0
FCR Bit-3 = 0
A-D S
11
T
Channel A selected
Channel B selected
Channel C selected
Channel D selected
UART de-selected
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
RANSMITTER FOR
R
ELECT IN
ECEIVER FOR
FCR B
FCR B
F
UNCTION
IT
IT
68 M
-0 = 1 (FIFO E
-0 = 1 (FIFO E
C
ODE
HANNELS
C
0 = FIFO below trigger level
1 = FIFO above trigger level
HANNELS
Figure 19
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO
empty
0 = FIFO above trigger level
1 = FIFO below trigger level or
transmitter empty
NABLED
NABLED
(DMA Mode Enabled)
(DMA Mode Enabled)
A-D
A-D
through 23.
FCR Bit-3 = 1
FCR Bit-3 = 1
)
)
Table 3 and 4
“Section 3.0,
XR16C864