xr16l2750im Exar Corporation, xr16l2750im Datasheet - Page 33

• Manufacturer Part Number: xr16l2750im
• Description: High-performance 2.25v - 5.5v Duart
• Manufacturer: Exar Corporation

xr
REV. 1.2.1
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count
Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is
suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1.
See
FC[7:0]: RX/TX FIFO Level Count
Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter
FIFO (FCTR[7] = 1) can be read via this register.
This register controls the XR16L2750 new functions that are not available in ST16C2450 or ST16C2550.
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
“0” to select the next trigger level for hardware flow control. See
FCTR[2]: IrDa RX Inversion
•
•
FCTR[3]: Auto RS-485 Direction Control
•
•
FCTR[5:4]: Transmit/Receive Trigger Table Select
See
4.15
4.16
4.17
4.18
Logic 0 = Select RX input as encoded IrDa data (Idle state will be LOW).
Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be HIGH).
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out.
Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from LOW to HIGH one bit time after the last stop bit of the last character is shifted out.
Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The
RTS# output pin will automatically return to a LOW when a data byte is loaded into the TX FIFO. However,
RTS# behavior can be inverted by setting EMSR[3] = 1.
Table
Table 10
Device Revision Register (DREV) - Read Only
Trigger Level Register (TRG) - Write-Only
RX/TX FIFO Level Count Register (FC) - Read-Only
Feature Control Register (FCTR) - Read/Write
12.
for more details.
FCTR
B
IT
0
0
1
1
-5
T
ABLE
FCTR
B
IT
0
1
0
1
-4
14: T
RIGGER
33
T
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
Table-D (TX/RX)
ABLE
T
ABLE
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
Table 13
S
ELECT
for more details.
XR16L2750