xr16l2552im Exar Corporation, xr16l2552im Datasheet - Page 12
xr16l2552im
Manufacturer Part Number
xr16l2552im
Description
Industry Smallest Package Uart With 2.25v To 5.5v Operation
Manufacturer
Exar Corporation
Datasheet
1.XR16L2552IM.pdf
(47 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
xr16l2552im-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
xr16l2552im-F
Manufacturer:
EXAR/艾科嘉
Quantity:
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when the FIFO and the TSR
become empty.
2.12
2.12.1
2.12.2
2.12.3
O
UTPUT
MCR Bit-7=0
153.6k
230.4k
460.8k
921.6k
Transmitter
Data Rate
Transmit Holding Register (THR) - Write Only
Transmitter Operation in non-FIFO Mode
Transmitter Operation in FIFO Mode
F
IGURE
T
ABLE
Clock
16X
7. T
5: T
Clock (Decimal)
D
RANSMITTER
Data
IVISOR FOR
Byte
YPICAL DATA RATES WITH A
6
4
2
1
Transmit Shift Register (TSR)
16x
O
PERATION IN NON
D
IVISOR FOR
Transmit
Clock (HEX)
Register
Holding
(THR)
06
04
02
01
14.7456 MH
16x
12
-FIFO M
DLM P
V
ALUE
ODE
THR Interrupt (ISR bit-1)
Z CRYSTAL OR EXTERNAL CLOCK
00
00
00
00
Enabled by IER bit-1
ROGRAM
(HEX)
M
S
B
DLL P
V
ALUE
06
04
02
01
ROGRAM
(HEX)
TXNOFIFO1
L
S
B
xr
D
E
ATA
RROR
REV. 1.1.1
0
0
0
0
R
ATE
(%)