xr16v598 Exar Corporation, xr16v598 Datasheet - Page 35

• Manufacturer Part Number: xr16v598
• Description: 2.25v To 3.6v High Performance Octal Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.2
]
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
ISR[5:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See
4.4.1, Interrupt Generation:” on page 34
ISR[0]: Interrupt Status
•
•
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last
applies to both the RX and TX side.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO interrupt. The UART will issue a transmit interrupt when
the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that
the FIFO did not get filled over the trigger level on last re-load.
4.5
P
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (default condition)
L
RIORITY
EVEL
X
1
2
3
4
5
6
7
FIFO Control Register (FCR) - Write Only
B
IT
0
0
0
0
0
0
1
0
-5
B
IT
0
0
0
0
0
1
0
0
-4
ISR R
B
T
EGISTER
IT
0
0
1
0
0
0
0
0
ABLE
-3
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
13: I
B
S
IT
TATUS
1
1
1
0
0
0
0
0
-2
NTERRUPT
and
B
B
ITS
IT
“Section 4.4.2, Interrupt Clearing:” on page 34
1
0
0
1
0
0
0
0
-1
S
OURCE AND
35
B
IT
0
0
0
0
0
0
0
1
-0
Table 14
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data Time-out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xon/Xoff or Special character)
CTS#/DSR#, RTS#/DTR# change of state
None (default) or wake-up indicator
P
RIORITY
Table 14
below shows the selections.
L
S
EVEL
OURCE OF THE INTERRUPT
shows the complete selections.
Table
13). See
XR16V598
for details.
“Section