xr16v598 Exar Corporation, xr16v598 Datasheet - Page 34

• Manufacturer Part Number: xr16v598
• Description: 2.25v To 3.6v High Performance Octal Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

XR16V598
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
IER[0]: RX Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
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The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others queue up for next
service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source
Table,
associated with each of these interrupt levels.
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4.4
4.4.1
4.4.2
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
LSR is by any of the LSR bits 1, 2, 3 and 4. See IER bit-2 description above.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS#/DSR# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS/DSR flow
control enabled by EFR bit-7 and selection on MCR bit-2.
RTS#/DTR# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS/DTR flow
control enabled by EFR bit-6 and selection on MCR bit-2.
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
Special character interrupt is cleared by a read to ISR or after the next character is received.
RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register.
Table
Interrupt Status Register (ISR) - Read Only
Interrupt Generation:
Interrupt Clearing:
13, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources
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REV. 1.0.2