xr16m752im48 Exar Corporation, xr16m752im48 Datasheet - Page 24

• Manufacturer Part Number: xr16m752im48
• Description: Xr68m752 -high Performance Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
A
SEE”RECEIVER” ON PAGE 15.
SEE”TRANSMITTER” ON PAGE 13.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
4.3.1
A2-A0
DDRESS
0 0 0
0 0 1
0 1 0
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
T
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
ABLE
XON1 RD/WR
XON2 RD/WR
XOFF
XOFF
N
DLM RD/WR
DLD RD/WR IR Mode
EFR RD/WR
R
DLL RD/WR
IER versus Receive FIFO Interrupt Mode Operation
AME
1
2
EG
8: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR
R
W
EAD
RITE
/
Enable
B
Bit-7
Bit-7
Auto
CTS
Bit-7
Bit-7
Bit-7
Bit-7
IT
-7
Auto RTS
Direction
Control
RS485
Enable
B
Bit-6
Bit-6
Auto
Bit-6
Bit-6
Bit-6
Bit-6
IT
-6
Baud Rate Generator Divisor
4X Mode 8X Mode
Special
Select
B
Bit-5
Bit-5
Char
Bit-5
Bit-5
Bit-5
Bit-5
Enhanced Registers
IT
-5
MCR[7:5],
FCR[5:4],
IER [7:4],
ISR [5:4],
Enable
24
B
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
DLD
IT
-4
S
HADED BITS ARE ENABLED WHEN
B
ware
Bit-3
Bit-3
Bit-3
Soft-
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
IT
-3
B
ware
Bit-2
Bit-2
Bit-2
Soft-
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
IT
-2
B
Bit-1
Bit-1
Bit-1
Soft-
ware
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Cntl
IT
-1
B
ware
Bit-0
Bit-0
Bit-0
Soft-
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Cntl
EFR B
IT
-0
IT
-4=1
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR=0
C
LCR[7]=1
LCR[7]=1
EFR[4]=1
REV. 1.0.2
OMMENT
X
BF