xr16m2650im48 Exar Corporation, xr16m2650im48 Datasheet - Page 26

• Manufacturer Part Number: xr16m2650im48
• Description: High Performance Low Voltage Duart With 32-byte Fifo
• Manufacturer: Exar Corporation

XR16M2650
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO
ISR[0]: Interrupt Status
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ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
Table
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to HIGH. ISR bit-4 indicates that the receiver detected a data match of
the Xoff character(s). If this is an Xoff/Xon interrupt, it can be cleared by a read to the ISR. If it is a special
character interrupt, it can be cleared by reading ISR or it will automatically clear after the next character is
received.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to HIGH. ISR bit-5 indicates that the CTS# or RTS# has been de-
asserted.
ISR[7:6]: FIFO Enable Status
These bits are set to LOW when the FIFOs are disabled. They are set to HIGH when the FIFOs are enabled.
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
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FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
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FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
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FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
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4.5
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to HIGH when other FCR bits are
written or they will not be programmed.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers (the receive shift register is not cleared or altered). This bit will
return to LOW after resetting the FIFO.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers (the transmit shift register is not cleared or altered). This bit will
return to LOW after resetting the FIFO.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
10).
FIFO Control Register (FCR) - Write-Only
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REV. 1.0.2