xr16m554 Exar Corporation, xr16m554 Datasheet - Page 13

• Manufacturer Part Number: xr16m554
• Description: 1.62v To 3.63v Quad Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.0
The M554 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Section 2.8, Programmable Baud Rate Generator” on page 13.
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown
in
generator for standard or custom rates. For further reading on oscillator circuit please see application note
DAN108 on EXAR’s web site.
Each UART has its own Baud Rate Generator (BRG) for the transmitter and receiver. The BRG further divides
this clock by a programmable divisor between 1 and (2
16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter for data bit
shifting and receiver for data sampling. The BRG divisor defaults to the maximum baud rate (DLL = 0x01 and
DLM = 0x00) upon power up and reset. Programming the Baud Rate Generator Registers DLL and DLM
provides the capability for selecting the operating data rate.
with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used (MCR bit-7 = 1), the output
data rate will be 4 times less than that shown in
F
2.7
2.8
IGURE
Figure
RXRDY#
TXRDY#
P
INS
5. T
Crystal Oscillator or External Clock Input
Programmable Baud Rate Generator
5. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate
T
YPICAL
ABLE
LOW = 1 byte
HIGH = no data
LOW = THR empty
HIGH = byte in THR
(FIFO D
5: TXRDY#
FCR
C
RYSTAL
BIT
ISABLED
-0=0
C
AND
ONNECTIONS
)
RXRDY# O
LOW = at least 1 byte in FIFO
HIGH = FIFO empty
LOW = FIFO empty
HIGH = at least 1 byte in FIFO
(DMA M
22-47pF
XTAL1
FCR B
C1
UTPUTS IN
ODE
R=300K to 400K
Table
IT
-3 = 0
D
14.7456
ISABLED
MHz
13
6.
16
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
FIFO
- 0.0625) in increments of 0.0625 (1/16) to obtain a
FCR B
)
22-47pF
XTAL2
Table 6
C2
AND
IT
HIGH to LOW transition when FIFO reaches the
trigger level, or timeout occurs
LOW to HIGH transition when FIFO empties
LOW = FIFO has at least 1 empty location
HIGH = FIFO is full
-0=1 (FIFO E
DMA M
shows the standard data rates available
ODE FOR
(DMA M
NABLED
FCR B
C
ODE
)
HANNELS
XR16M554/554D
IT
-3 = 1
E
NABLED
A-D
)