xr16m554 Exar Corporation, xr16m554 Datasheet - Page 12

• Manufacturer Part Number: xr16m554
• Description: 1.62v To 3.63v Quad Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

XR16M554/554D
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
Each UART channel in the M554 has a set of enhanced registers for controlling, monitoring and data loading
and unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratchpad register (SPR). All the register functions are discussed in full detail later in
UART INTERNAL REGISTERS” on page
The interrupt outputs change according to the operating mode and enhanced features setup.
summarize the operating behavior for the transmitter and receiver. Also see
The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A-D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide
additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the
transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit
and receive FIFO in the DMA mode (FCR bit-3 = 1). When the transmit and receive FIFOs are enabled and the
DMA mode is disabled (FCR bit-3 = 0), the M554 is placed in single-character mode for data transmit or
receive operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode
operation by loading or unloading the FIFO in a block sequence determined by the programmed trigger level.
The following table show their behavior. Also see
2.4
2.5
2.6
INT Pin
INT Pin
Channels A-D Internal Registers
INT Ouputs for Channels A-D
DMA Mode
LOW = a byte in THR
HIGH = THR empty
LOW = no data
HIGH = 1 byte
(FIFO D
(FIFO D
FCR B
FCR B
T
ABLE
T
ABLE
IT
ISABLED
IT
ISABLED
-0 = 0
-0 = 0
3: INT P
4: INT P
)
)
IN
IN
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or
FIFO empty
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
O
PERATION FOR
O
PERATION FOR
19.
(DMA Mode Disabled)
(DMA Mode Disabled)
Figure 18
FCR Bit-3 = 0
FCR Bit-3 = 0
12
T
RANSMITTER FOR
R
ECEIVER FOR
FCR B
FCR B
through 23.
IT
IT
-0 = 1 (FIFO E
-0 = 1 (FIFO E
C
HANNELS
C
HANNELS
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or
FIFO empty
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
Figure 18
NABLED
NABLED
(DMA Mode Enabled)
(DMA Mode Enabled)
A-D
A-D
FCR Bit-3 = 1
FCR Bit-3 = 1
through 23.
)
)
Table 3 and 4
“Section 3.0,
REV. 1.0.0