ICS502 Integrated Circuit System, ICS502 Datasheet - Page 3

• Manufacturer Part Number: ICS502
• Description: Loco (tm) PLL Clock Multiplier
• Manufacturer: Integrated Circuit System

MDS 502 E
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA •9 5126 • [phone]te l • www.icst.com
Electrical Specifications
Parameter
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Inputs
Clock Output
Ambient Operating Temperature
Soldering Temperature
Storage temperature
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
Input High Voltage, VIH, ICLK only
Input Low Voltage, VIL, ICLK only
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
IDD Operating Supply Current, 20 MHz crystal
Short Circuit Current
On-Chip Pull-up Resistor
Input Capacitance, S1, S0
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency, VDD = 4.5 to 5.5V
Output Frequency, VDD = 3.0 to 3.6V
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Conditions
Referenced to GND
Referenced to GND
Referenced to GND
ICS502MI only
Max of 10 seconds
ICLK (Pin 1)
ICLK (Pin 1)
S0
S0
S1
S1
IOH=-25mA
IOL=25mA
No Load, 100MHz
CLK output
Pin 6
Pins 6, 7
0 C to +70 C
-40 C to +85 C
0 C to +70 C
-40 C to +85 C
0.8 to 2.0V
2.0 to 0.8V
at VDD/2
Deviation from mean
3
LOCO™ PLL Clock Multiplier
Minimum
(VDD/2)+1
VDD-0.5
-0.5
-0.5
-40
-65
2.4
14
14
14
14
45
0
3
2
5
2
Typical
49 to 51
VDD/2
VDD/2
±120
±70
270
20
50
4
1
1
Maximum
(VDD/2)-1
VDD+0.5
VDD+0.5
260
150
160
140
100
5.5
0.8
0.5
0.4
70
85
27
50
90
55
7
Revision 021402
ICS502
Units
MHz
MHz
MHz
MHz
MHz
MHz
mA
mA
k
pF
ns
ns
ps
ps
%
V
V
V
C
C
C
C
V
V
V
V
V
V
V
V
V