sp5055 Mitel, sp5055 Datasheet - Page 3

• Manufacturer Part Number: sp5055
• Description: 2.6ghz Bidirectional I2c Bus Controlled Synthesiser
• Manufacturer: Mitel

FUNCTIONAL DESCRIPTION
Clock are fed in on the SDA and SCL lines respectively as
defined by the I
accept new data (write mode) or send data (read mode). The
Tables in Fig. 3 illustrate the format of the data. The device
can be programmed to respond to several addresses, which
enables the use of more than one synthesiser in an I
system. Table 4 shows how the address is selected by
applying a voltage to P3. The last bit of the address byte
(R/W) sets the device into read mode if it is high and write
mode if it is low. When the SP5055 receives a correct address
byte it pulls the SDA line low during the acknowledge period
and during following acknowledge periods after further data
bytes are programmed. When the SP5055 is programmed
into the read mode the controlling device accepting the data
must pull down the SDA line during the following acknowledge
period to read another status byte.
WRITE MODE (FREQUENCY SYNTHESIS)
synthesised frequency while bytes 4 + 5 select the output port
states and charge pump information.
the first Bit of the next Byte determines whether that byte is
interpreted as byte 2 or 4, a logic 0 for frequency information
and a logic 1 for charge pump and output port information.
Additional data bytes can be entered without the need to
re-address the device until an I
This allows a smooth frequency sweep for fine tuning or AFC
purposes.
another device on the bus) then the previously programmed
byte is maintained.
register and is used to control the division ratio of the 15-bit
programmable divider which is preceded by a divide-by-16
prescaler and amplifier to give excellent sensitivity at the local
oscillator input; see Fig 5. The input impedance is shown in
Fig 7.
The SP5055 is programmed from an I
When the device is in the write mode Bytes 2 + 3 select the
Once the correct address is received and acknowledged,
If the transmission of data is stopped mid-byte (i.e., by
Frequency data from bytes 2 and 3 is stored in a 15-bit shift
2
C BUS format. The synthesiser can either
2
C stop condition is recognised.
2
C BUS. Data and
Fig. 2 Block diagram
2
C Bus
multiplying the programmed division ratio by 16 times the
comparison frequency F
via the charge pump and varactor drive amplifier, adjusts the
local oscillator control voltage until the output of the
programmable divider is frequency and phase locked to the
comparison frequency.
source capacitively coupled into pin 2 or provided by an on-
board 4MHz crystal controlled oscillator.
4MHz reference is used.
current in the charge pump circuit, a logic 1 for ±170µA and
a logic 0 for ±50µA, allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. Bit 4 of byte 4 (T0) disables the
charge pump if set to a logic 1. Bit 8 of byte 4 (OS) switches
the charge pump drive amplifier’s output off when it is set to
a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the
phase comparator inputs are available on P6 and P7, a logic
1 connects F
a high impedance output, logic 1 for low impedance (on).
READ MODE
the device on the SDA line takes the form shown in Table 2.
1 if the power supply to the device has dropped below 3V and the
programmed information lost (e.g., when the device is initially
turned on). The POR is set to 0 when the read sequence is
terminated by a stop command. The outputs are all set to high
impedance when the device is initially powered up. Bit 2 (FL)
indicates whether the device is phase locked, a logic 1 is present
if the device is locked and a logic 0 if the device is unlocked.
The programmed frequency can be calculated by
When frequency data is entered, the phase comparator,
The reference frequency may be generated by an external
Note that the comparison frequency is 7·8125kHz when a
Bit 2 of byte 4 of the programming data (CP) controls the
Byte 5 programs the output ports P0 to P7; on a logic 0 for
When the device is in the read mode the status data read from
Bit 1 (POR) is the power-on reset indicator and is set to a logic
comp
to P6 and F
comp
.
div
to P7.
3