ak4395 AKM Semiconductor, Inc., ak4395 Datasheet - Page 18

• Manufacturer Part Number: ak4395
• Description: Advanced Multi-bit 192khz 24-bit ?? Dac
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4395. For DIF0/1/2, the
setting of pin and register are “ORed” internally. So, even serial control mode, these functions can be also controlled by pin
setting.
The serial control interface is enabled by the P/S pin = “L”. In this mode, pin setting must be all “L”. Internal registers may
be written by 3-wire µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2bits,
CAD0/1), Read/Write (1bit; fixed to “1”), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). The
AK4395 latches the data on the rising edge of CCLK, so data should be clocked in on the falling edge. The writing of data
becomes valid by CSN “ ”. The clock speed of CCLK is 5MHz (max). The CSN and CCLK must be fixed to “H” when the
register does not be accessed.
PDN = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4395 should be reset by
PDN = “L”. In serial mode, the internal timing circuit is reset by RSTN bit, but the registers are not initialized.
*When the AK4395 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register
*For setting the registers, the following sequence is recommended.
MS0040-E-01
is inhibited.
Mode Control Interface
Control 1 register
Control 2 register
(1) Writing RSTN = “0” and other bits (D7-D1) to the register at the same time.
(2) Writing RSTN = “1” to the register. The other bits are no change.
This writing sequence has no limitation like control 1 register.
When setting DEM0/1 and SMUTE, RSTN is not needed.
CCLK
CSN
CDTI
C1
Function
Auto Setting Mode
Manual Setting Mode
De-emphasis
SMUTE
Zero Detection
Slow roll-off response
Digital Attenuator
0
Table 10. Function List (O: Available, X: Not available)
C0
1
R/W
2
C1-C0:
R/W:
A4-A0:
D7-D0:
A4
3
Figure 8. Control I/F Timing
A3
4
READ/WRITE (Fixed to “1”, Write only)
Chip Address (C1=CAD1, C0=CAD0)
Register Address
Control Data
A2
5
A1
6
- 18 -
Parallel mode
O (Partially)
A0
7
D7
O
O
O
X
X
X
8
D6
9
D5
10 11 12 13 14 15
D4
Serial mode
D3
O
O
O
O
O
O
O
D2
D1
D0
[AK4395]
2001/4