ak4390 ETC-unknow, ak4390 Datasheet - Page 28

• Manufacturer Part Number: ak4390
• Description: Ultra Low Latency 32-bit ?? Dac
• Manufacturer: ETC-unknow

1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively.
AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. Power lines of
AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc. The power up
sequence between AVDD and DVDD is not critical. VSS1/2/3/4 must be connected to the same analog ground
plane. Decoupling capacitors for high frequency should be placed as near as possible to the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the analog output range. The VREFHL/R pin is
normally connected to AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R and VREFLL/R
should be connected with a 0.1µF ceramic capacitor. All signals, especially clocks, should be kept away from the
VREFHL/R and VREFLL/R pins in order to avoid unwanted noise coupling into the AK4390.
3. Analog Outputs
The analog outputs are fully differential outputs at 2.8Vpp (typ, VREFHL/R − VREFLL/R = 5V), centered around
AVDD/2 (typ). The differential outputs are summed externally, V
AOUT−. If the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R − VREFLL/R = 5V). The bias voltage of
the external summing circuit is supplied externally. The input data format is two’s complement. The output voltage
(V
is 0V for 000000H(@24-bits).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband.
Figure 15
MS1046-E-00
AOUT
) is positive full scale for 7FFFFFH (@24-bits) and negative full scale for 800000H (@24-bits). The ideal V
shows an example of differential outputs and a LPF circuit example by three op-amps.
Figure 14
Digital Ground
shows an example of an external LPF circuit summing the differential outputs with an op-amp.
Controller
System
Figure 13. Ground Layout
- 28 -
AOUT
Analog Ground
= (AOUT+) − (AOUT−) between AOUT+ and
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
TST1/CAD0
DEM0/CCLK
DEM1/CDTI
DIF0/CAD1
DIF1/DZFL
DIF2
PSN
TST2/DZFR
AOUTRP
AOUTRN
VSS1
VDRR
VREFHR
VREFLR
SMUTE/CSN
AK4390
AOUTLP
AOUTLN
VREFHL
VREFLL
SDATA
DVDD
MCLK
AVDD
LRCK
VSS4
VSS3
VSS2
VDDL
BICK
PDN
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
[AK4390]
2009/01
AOUT