ak4390 ETC-unknow, ak4390 Datasheet - Page 21

• Manufacturer Part Number: ak4390
• Description: Ultra Low Latency 32-bit ?? Dac
• Manufacturer: ETC-unknow

(2) RESET by MCLK or LRCK stop
The AK4390 is automatically placed in reset state when MCLK or LRCK is stopped during normal operation and the
analog outputs are floating (Hi-Z). When MCLK and LRCK are input again, the AK4390 exits reset state and starts the
operation. Zero detect function is disable when MCLK or LRCK is stopped.
Notes:
MS1046-E-00
(1) After AVDD and DVDD are powered-up, the PDN pin should be held “L” for 150ns.
(2) The analog output corresponding to digital input has the group delay (GD).
(3) Digital data can be stopped. The click noise after MCLK and LRCK are input again can be reduced by inputting
(4) Click noise occurs in 3 ∼ 4LRCK cycles ether on a rising edge (↑) of the PDN signal or MCLK inputs. This noise
(5) Mute the analog output externally if click noise (4) influences system application. The timing example is shown in
Internal
D/A In
D/A Out
Clock In
MCLK, BICK, LRCK
RSTB pin
AVDD pin
DVDD pin
External
MUTE
(Digital)
(Analog)
State
the “0” data during this period.
is output even if “0” data is input.
this figure.
Power-down
Power-down
(1)
Hi-Z
(6)
(4)
Figure 10. Reset Sequence Example 2
Normal O peration
GD
(2)
- 21 -
(6)
MCLK, BICK, LRCK Stop
(4)
Digital Circuit P ower-down
(5)
(3)
(5)
(4)
(6)
Normal Operation
GD
(2)
[AK4390]
2009/01