ak4380 AKM Semiconductor, Inc., ak4380 Datasheet - Page 9

• Manufacturer Part Number: ak4380
• Description: 100db 24bit 96khz 2ch Dac
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
n System Clock
The external clocks, which are required to operate the AK4380, are MCLK, LRCK and BICK. The master clock (MCLK)
corresponds to 256fs, 384fs, 512fs or 768fs (for normal speed mode; 128fs, 192fs, 256fs or 384fs for double speed mode).
MCLK frequency is automatically detected, and the internal master clock becomes 256fs (for normal speed mode; 128fs
for double speed mode). The MCLK should be synchronized with LRCK but the phase is not critical. Table 1 3 illustrate
corresponding clock frequencies.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4380 is in the normal operation
mode (PDN= “H”). If these clocks are not provided, the AK4380 may draw excess current because the device utilizes
dynamic refreshed logic internally. The AK4380 should be reset by PDN= “L” after threse clocks are provided. If the
external clocks are not present, the AK4380 should be in the power-down mode (PDN= “L”). After exiting reset at
power-up etc., the AK4380 is in the power-down mode until MCLK and LRCK are input.
MS0018-E-01
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
LRCK
LRCK
fs
fs
DFS pin / DFS bit
LRCK Frequency (fs)
MCLK Frequency
11.2896MHz
12.2880MHz
11.2896MHz
12.2880MHz
8.1920MHz
256fs
128fs
Table 2. System clock example (Normal Speed Mode)
Table 3. System clock example (Double Speed Mode)
12.2880MHz
16.9344MHz
18.4320MHz
16.9344MHz
18.4320MHz
256fs,384fs,512fs,768fs
OPERATION OVERVIEW
384fs
192fs
Normal Speed Mode
Table 1. System clock
8kHz~48kHz
“L” / “0”
MCLK
MCLK
16.3840MHz
22.5792MHz
24.5760MHz
22.5792MHz
24.5760MHz
- 9 -
512fs
256fs
128fs,192fs,256fs,384fs
24.5760MHz
33.8688MHz
36.8640MHz
33.8688MHz
36.8640MHz
Double Speed Mode
768fs
384fs
8kHz~96kHz
“H” / “1”
2.0480MHz
2.8224MHz
3.0720MHz
5.6448MHz
6.1440MHz
BICK
BICK
64fs
64fs
[AK4380]
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